Datasheet
V
CCIO
80% 80%
20% 20%
0
Input
t
pw
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
SPNS141F–AUGUST 2010– REVISED JULY 2011
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7.7 Input Timings
7.7.1 Timing Requirements For Input Timings
Table 7-11. Timing Requirements For Input Timings
(1)
MIN MAX Unit
t
pw
Input minimum pulse width t
c(VCLK)
+ 10
(2)
ns
(1) t
c(VCLK)
= peripheral VBUS clock cycle time = 1 / f
(VCLK)
(2) The timing shown above is only valid for pin used in GIO mode
Figure 7-8. CMOS-Level Inputs
76 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated
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