Datasheet

3.3 V
1.5 V
CCIOPORL
PORRST
V
CC
(1.5 V)
6
V
CCPORH
V
V
IL(PORRST)
V
CCIOPORH
V
CCIOPORH
V
CCIOPORL
V
CCPORL
V
CC
V
CCIO
/ V
CCP
V
CCPORH
V
CCPORL
V
IL
V
IL
V
IL
V
IL
V
IL(PORRST)
8
7
6
3
7
9
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
www.ti.com SPNS141F–AUGUST 2010– REVISED JULY 2011
7.3 RST And PORRST Timings
7.3.1 Timing Requirements For PORRST
Table 7-6. Timing Requirements For PORRST
NO. MIN MAX Unit
V
CCPORL
V
CC
low supply level when PORRST must be active during power up 0.5 V
V
CCPORH
V
CC
high supply level when PORRST must remain active during power up 1.35 V
and become active during power down
V
CCIOPORL
V
CCIO
/ V
CCP
low supply level when PORRST must be active during 1.1 V
power up
V
CCIOPORH
V
CCIO
/ V
CCP
high supply level when PORRST must remain active during 3 V
power up and become active during power down
V
IL(PORRST)
Low-level input voltage of PORRST V
CCIO
> 2.5V 0.2 V
CCIO
V
Low-level input voltage of PORRST V
CCIO
< 2.5V 0.5 V
3 t
su(PORRST)
Setup time, PORRST active before V
CCIO
and V
CCP
> V
CCIOPORL
during 0 ms
power up
6 t
h(PORRST)
Hold time, PORRST active after V
CC
> V
CCPORH
1 ms
7 t
su(PORRST)
Setup time, PORRST active before V
CC
<= V
CCPORH
during power down 8 µs
8 t
h(PORRST)
Hold time, PORRST active after V
CCIO
and V
CCP
> V
CCIOPORH
1 ms
9 t
h(PORRST)
Hold time, PORRST active after V
CC
< V
CCPORL
0 ms
t
f(PORRST)
Filter time PORRST, pulses less than MIN will be filtered out, pulses 20 150 ns
greater than MAX are guaranteed to generate a reset
(1)
t
f(RST)
Filter time RST, pulses less than MIN will be filtered out, pulses greater 20 150 ns
than MAX are guaranteed to generate a reset
(1) A low pulse on the nPORRST pin which is just barely longer than the glitch filter implemented on this pin will result in a very short
internal reset. This may result in unpredictable behavior as some parts of the device may be reset while other parts of the device are
not.
Figure 7-5. PORRST Timing Diagram
NOTE
There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage;
this is just an exemplary drawing. All requirements are to ensure PORRST is active when
VCCIO or VCC is out of the normal operating range.
Copyright © 2010–2011, Texas Instruments Incorporated Peripheral and Electrical Specifications 71
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