Datasheet

ECLK
3
4
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
SPNS141F–AUGUST 2010– REVISED JULY 2011 www.ti.com
7.2 ECLK Specification
7.2.1 Switching Characteristics Over Recommended Operating Conditions For External
Clocks
Table 7-5. Switching Characteristics Over Recommended Operating Conditions For External Clocks
(1)(2)
NO. Parameter Test Conditions MIN MAX Unit
3 t
w(EOL)
Pulse duration, ECLK low under all prescale factor 0.5t
c(ECLK)
– tf ns
combinations (X and N)
4 t
w(EOH)
Pulse duration, ECLK high under all prescale factor 0.5t
c(ECLK)
– ns
combinations (X and N) tr
(1) X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the VBUS interface clock divider ratio determined by the CLKCNTL.[19:16] bits in the
SYS module.
(2) N = {1 to 65536}. N is the ECP prescale value defined by the ECPCNTL.[15:0] register bits in the System module.
Figure 7-4. ECLK Timing Diagram
70 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated
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