Datasheet
Address Waitstates
Data Waitstates
RAM
Address Waitstates
Data Waitstates
Flash
0MHz
0MHz
0MHz
0MHz
f(HCLK)
f(HCLK)
f(HCLK)
f(HCLK)
100MHz
108MHz
72MHz
36MHz
0
1
2
3
0
1
0
0
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
www.ti.com
SPNS141F–AUGUST 2010– REVISED JULY 2011
7.1.5 Switching Characteristics Over Recommended Operating Conditions For Clocks
Table 7-4. Switching Characteristics Over Recommended Operating Conditions For Clocks
Parameter Test Conditions MIN MAX Unit
f
(HCLK)
HCLK - System clock frequency (337 BGA Pipeline mode enabled 160 MHz
packages)
Pipeline mode disabled 36 MHz
f
(HCLK)
HCLK - System clock frequency (144pin QFP Pipeline mode enabled 140 MHz
package)
Pipeline mode disabled 36 MHz
f
(GCLK)
GCLK - CPU clock frequency (ratio GCLK : f
(HCLK)
MHz
HCLK = 1:1)
f
(RCLK)
RCLK - Frequency out of PLL macro into 160 MHz
R-divider
f
(RTICLK)
(1)
RTICLK - clock frequency f
(VCLK)
MHz
f
(VCLK)
VCLK - Primary peripheral clock frequency f
(VCLK2)
MHz
f
(VCLK2)
VCLK2 - Secondary peripheral clock frequency 100 MHz
f
(AVCLK1)
AVCLK1 - Primary asynchronous peripheral clock f
(VCLK)
MHz
frequency
f
(AVCLK2)
AVCLK2 - Secondary asynchronous peripheral f
(VCLK)
MHz
clock frequency
f
(ECLK)
(2)
ECLK - External clock output frequency for ECP 80 MHz
Module
f
(PROG/ERASE)
System clock frequency - Flash f
(HCLK)
MHz
programming/erase
(1) If the RTIx clock source is chosen to be anything other than the default VCLK, then the RTI clock needs to be at least three times slower
than the VCLK.
(2) (ECLK) = f(VCLK) / N, where N = {1 to 65536}. N is the ECP prescale value defined by the ECPCNTL.[15:0] register bits in the System
module. Pipeline mode enabled or disabled is determined by the FRDCNTL[2:0].
7.1.5.1 Timing - Wait States
Figure 7-3. Wait States
NOTE
If FMzPLL frequency modulation is enabled, special care must be taken to ensure that the
maximum system clock frequency f(HCLK) and peripheral clock frequency f(VCLK) are not
exceeded. The speed of the device clocks may need be derated to accommodate the
modulation depth when FMzPLL frequency modulation is enabled.
Copyright © 2010–2011, Texas Instruments Incorporated Peripheral and Electrical Specifications 69
Submit Documentation Feedback
focus.ti.com: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116
TMS570LS10106