Datasheet

TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
SPNS141F–AUGUST 2010– REVISED JULY 2011 www.ti.com
4.7 ETM
The device contains an ARM Cortex™-R4F External Trace Macrocell (ETM-R4) with a 32bit data port. The
ETM-R4 module is connected to a Test Port Interface Unit (TPIU) with a 32bit data bus. The ETM-R4 is
CoreSight compliant and follows the ARM ETM v3 specification; for more details see ARM CoreSight™
ETM-R4 TRM specification Revr0p0. The ETM-R4 supports "half rate clocking" only.
The ETM clock source can be selected as either VCLK or the external ETMTRACECLKIN pin. The
selection is done by the EXTCTRLOUT[1:0] control bits of the TPIU; the default is '00'.
Table 4-12. ETMTRACECLKIN Selection
EXTCTRLOUT[1:0] TPIU/TRACECLKIN
00 tied-zero
01 VCLK
10 ETMTRACECLKIN
11 tied-zero
50 Peripherals Copyright © 2010–2011, Texas Instruments Incorporated
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