Datasheet

Flash
2.0MB
with ECC
CRC
OSC
NHET
SYS
LIN2
MiBSPI1
DCAN1
OSCIN
OSCOUT
TRST
TMS
TCK
TDI
TDO
RST
PORRST
TEST
NHET[31:0]
LIN2RX
LIN2TX
MIBSPI1SIMO
MIBSPI1SOMI
MIBSPI1CLK
MIBSPI1SCS[3:0]
CAN1RX
CAN1TX
FLTP1
ECLK
MIBSPI3SIMO
MIBSPI3SOMI
MIBSPI3CLK
DCAN2
CAN2RX
CAN2TX
128 Words
128 Buffers
MIBSPI3SCS[3:0]
VIM
HET TU
8 DCP
64 Messages
64 Messages
DMA
16 Channels
Primary SCR
ETM
ETMTRACECTL
ETMTRACECLKOUT
CCM-R4
RTP
DMM
RTCK
RTPDATA[15:0]
RTPSYNC
RTPCLK
1 Port
MIBSPI1ENA
with Parity
with Parity
with Parity
with Parity
V
CCP1
with Parity
with MPU
ETMDATA[31:0]
MIBSPI3ENA
FLTP2
with MPU
RTPENA
8 Transfer
Groups
64 Channel
with Parity
2 Channel
Clock
Monitor
MiBSPI3
128 Buffers
with Parity
8 Transfer
Groups
FlexRay
8k Byte
with Parity
FRAYRX1
FRAYTX1
FRAYTXEN1
FRAYRX2
FRAYTX2
FRAYTXEN2
DCAN3
CAN3RX
CAN3TX
32 Messages
with Parity
RAM
160kB
with ECC
FMzPLL
Kelvin_GND
DAP
DMMENA
DMMSYNC
DMMCLK
DMMDATA[1:0]
with Parity
Periph Bridge
Cortex-R4F
Msg RAM
FlexRay
with MPU
with Parity
RTI
SCR
2
TU
SCR
1
Note:
Priorities
SCR2 : round robin
SCR : round robin
SCR1 : 1=DMA, 2=DMM, 3=DAP
DMMDATA[15:2]*
MiBADC2
64 Words
with Parity
AD2IN[7:0]
AD2EVT
MiBSPIP5
MIBSPI5SIMO[3:0]*
MIBSPI5SOMI[3:0]*
MIBSPI5CLK*
MIBSPI5SCS[3:0]*
MIBSPI5ENA*
128 Buffers
with Parity
8 Transfer
Groups
32 Regions
with DMMDATA[15:2] pins
64 Words
with
ICEPick
2 RAM blocks
ESM
ERROR
MiBADC1
64 Words
with Parity
AD1IN[7:0]
V
SSAD
AD
REFHI
AD
REFLO
AD1EVT
12Bit
12Bit
with MPU
Cortex-R4F
with MPU
GIO
GIOA[7:0]/INT[7:0]
GIOB[7:0]
LIN1
LIN1RX
LIN1TX
STC
LBIST
EMIFADD[21:0]
EMIFDATA[15:0]
EMIFCS[3:0]
EMIFWE
EMIFOE
EMIF
EMIFBADD[1:0]
V
CCAD
ADSIN[15:8]
P
O
M
* MIBSPIP5 pins are multiplexed
ETMTRACECLKIN
EMIFDQM[1:0]
SCR
PCR
FPLL
for FlexRay
VMON
VccIO
Vcc
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
www.ti.com SPNS141F–AUGUST 2010– REVISED JULY 2011
1.3 Functional Block Diagram
Copyright © 2010–2011, Texas Instruments Incorporated TMS570LS Series 16/32-BIT RISC Flash Microcontroller 5
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TMS570LS10106