Datasheet

TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
www.ti.com SPNS141F–AUGUST 2010– REVISED JULY 2011
4.4 Vectored Interrupt Manager (VIM)
The Vectored Interrupt Manager (VIM) provides hardware assistance for prioritizing and controlling the
many interrupt sources present on the device. Interrupt requests originating from the device modules (i.e.,
SPI, LIN, SCI, etc.) are assigned to channels within the 64-channel VIM. Programming multiple interrupt
sources to the same VIM channel effectively shares the VIM channel between sources. The VIM request
channels are maskable so that individual channels can be selectively disabled. All interrupt requests can
be programmed in the VIM to be of either type:
• Fast interrupt request (FIQ)- The FIQ implemented in Cortex-R4F is Non-Maskable Fast Interrupts
(NMFI).
• Normal interrupt request (IRQ)
The VIM prioritizes interrupts, whose precedence of request channels decrease with ascending channel
order in the VIM (0 [highest] and 64[lowest] priority). For VIM default mapping, channel priorities, and their
associated modules see the table below. More information on the VIM can be found in the technical
reference manual (TRM).
Table 4-5. Interrupt Request Assignments
Modules Interrupt Sources Default VIM Interrupt Request
ESM ESM High level interrupt (NMI) 0
Reserved (NMI) 1
RTI RTI compare interrupt 0 2
RTI RTI compare interrupt 1 3
RTI RTI compare interrupt 2 4
RTI RTI compare interrupt 3 5
RTI RTI overflow interrupt 0 6
RTI RTI overflow interrupt 1 7
RTI RTI timebase 8
GIO GIO interrupt A 9
NHET NHET level 1 interrupt 10
HET TU HET TU level 1 interrupt 11
MIBSPI1 MIBSPI1 level 0 interrupt 12
LIN1 (incl. SCI) LIN1 level 0 interrupt 13
MIBADC1 MIBADC1 event group interrupt 14
MIBADC1 MIBADC1 sw group 1 interrupt 15
DCAN1 DCAN1 level 0 interrupt 16
Reserved Reserved 17
FlexRay FlexRay level 0 interrupt 18
CRC CRC Interrupt 19
ESM ESM Low level interrupt 20
SYSTEM Software interrupt (SSI) 21
CPU PMU Interrupt 22
GIO GIO interrupt B 23
NHET NHET level 2 interrupt 24
HET TU HET TU level 2 interrupt 25
MIBSPI1 MIBSPI1 level 1 interrupt 26
LIN1 (incl. SCI) LIN1 level 1 interrupt 27
MIBADC1 MIBADC1 sw group 2 interrupt 28
DCAN1 DCAN1 level 1 interrupt 29
Reserved Reserved 30
MIBADC1 MIBADC1 magnitude interrupt 31
Copyright © 2010–2011, Texas Instruments Incorporated Peripherals 45
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