Datasheet
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
www.ti.com
SPNS141F–AUGUST 2010– REVISED JULY 2011
4.2 Direct Memory Access (DMA)
The direct-memory access (DMA) controller transfers data to and from any specified location in the device
memory map. The DMA supports data transfer for both on-chip memories and peripherals.
The DMA controller on this device supports 16 channels and 32 request lines. Each of the 32 DMA
requests are assigned by default to one of the 16 available channels. For DMA requests multiplexed
between multiple sources, the DMA controller cannot differentiate between the multiple sources and the
user has to ensure that multiple sources are not enabled at the same time. Please refer to the DMA
Specification in the TRM for more details.
The DMA request configuration is shown in the following table.
Table 4-3. DMA Request Line Connection
Modules DMA Request Sources DMA Request
MIBSPI1 MIBSPI1[1]
(1)
DMAREQ[0]
MIBSPI1 MIBSPI1[0]
(2)
DMAREQ[1]
Reserved Reserved DMAREQ[2]
Reserved Reserved DMAREQ[3]
MIBSPI1 / MIBSPI3 / DCAN2 MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3 DMAREQ[4]
MIBSPI1 / MIBSPI3 / DCAN2 MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2 DMAREQ[5]
MIBSPIP5 / DCAN1 MIBSPIP5[2] / DCAN1 IF2 DMAREQ[6]
MIBADC1 / MIBSPIP5 MIBADC1 event / MIBSPIP5[3] DMAREQ[7]
MIBSPI1 / MIBSPI3 / DCAN1 MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1 DMAREQ[8]
MIBSPI1 / MIBSPI3 / DCAN2 MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1 DMAREQ[9]
MIBADC1 / MIBSPIP5 MIBADC1 G1 / MIBSPIP5[4] DMAREQ[10]
MIBADC1 / MIBSPIP5 MIBADC1 G2 / MIBSPIP5[5] DMAREQ[11]
RTI / MIBSPI1 / MIBSPI3 RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6] DMAREQ[12]
RTI / MIBSPI1 / MIBSPI3 RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7] DMAREQ[13]
MIBADC2 / MIBSPI3 / MIBSPIP5 MIBADC2 event / MIBSPI3[1]
(1)
/ MIBSPIP5[6] DMAREQ[14]
MIBSPI3 / MIBSPIP5 MIBSPI3[0]† / MIBSPIP5[7] DMAREQ[15]
MIBADC2 / MIBSPI1 / MIBSPI3 / DCAN1 MIBADC2 G1 / MIBSPI1[8] / MIBSPI3[8] / DCAN1 DMAREQ[16]
IF3
MIBADC2 / MIBSPI1 / MIBSPI3 / DCAN3 MIBADC2 G2 / MIBSPI1[9] / MIBSPI3[9] / DCAN3 DMAREQ[17]
IF1
RTI / MIBSPIP5 RTI DMAREQ2 / MIBSPIP5[8] DMAREQ[18]
RTI / MIBSPIP5 RTI DMAREQ3 / MIBSPIP5[9] DMAREQ[19]
LIN2 / NHET / DCAN3 LIN2 receive / NHET DMAREQ[4] / DCAN3 IF2 DMAREQ[20]
LIN2 / NHET / DCAN3 LIN2 transmit / NHET DMAREQ[5] / DCAN3 IF3 DMAREQ[21]
MIBSPI1 / MIBSPI3 / MIBSPIP5 MIBSPI1[10] / MIBSPI3[10] / MIBSPIP5[10] DMAREQ[22]
MIBSPI1 / MIBSPI3 / MIBSPIP5 MIBSPI1[11] / MIBSPI3[11] / MIBSPIP5[11] DMAREQ[23]
NHET / MIBSPIP5 NHET DMAREQ[6] / MIBSPIP5[12] DMAREQ[24]
NHET / MIBSPIP5 NHET DMAREQ[7] / MIBSPIP5[13] DMAREQ[25]
CRC / MIBSPI1 / MIBSPI3 CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12] DMAREQ[26]
CRC / MIBSPI1 / MIBSPI3 CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13] DMAREQ[27]
LIN1 / MIBSPIP5 LIN1 receive / MIBSPIP5[14] DMAREQ[28]
LIN1 / MIBSPIP5 LIN1 transmit / MIBSPIP5[15] DMAREQ[29]
MIBSPI1 / MIBSPI3 / MIBSPIP5 MIBSPI1[14] / MIBSPI3[14] / MIBSPIP5[1]
(1)
DMAREQ[30]
MIBSPI1 / MIBSPI3 / MIBSPIP5 MIBSPI1[15] / MIBSPI3[15] / MIBSPIP5[0]
(2)
DMAREQ[31]
(1) SPI1, SPI3, SPI5 receive in standard SPI/compatibility mode
(2) SPI1, SPI3, SPI5 transmit in standard SPI/compatibility mode
Copyright © 2010–2011, Texas Instruments Incorporated Peripherals 43
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