Datasheet

TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
www.ti.com SPNS141F–AUGUST 2010– REVISED JULY 2011
3 Reset / Abort Sources
3.1 Reset / Abort Sources
The device Resets and Aborts are handled as shown in the following table. The table shows the source of
the error, the system mode, the type of error response and the corresponding Error Signaling Module
(ESM) channel. Only standard ARM exception handlers and ESM errors are used.
Table 3-1. Reset / Abort Sources
Error Source System Mode Error Response ESM Hookup group channel
1) CPU transactions
Precise write error (Strongly User/Privilege Precise Abort (CPU) n/a
Ordered)
Precise read error (Device or User/Privilege Precise Abort (CPU) n/a
Normal)
Imprecise write error (Device or User/Privilege Imprecise Abort (CPU) n/a
Normal)
Illegal instruction User/Privilege Undefined Instruction Trap n/a
(CPU)
(1)
MPU access violation User/Privilege Abort (CPU) n/a
2) SRAM
B0 Tightly Coupled Memory User/Privilege ESM 1.26
(TCM) (even) ECC single error
(correctable)
B0 TCM (even) ECC double error User/Privilege Abort (CPU), ESM => nERROR 3.3
(non-correctable)
B0 TCM (even) uncorrectable User/Privilege ESM => NMI 2.6
error (i.e. redundant address
decode)
B0 TCM (even) address bus User/Privilege ESM => NMI 2.10
parity error
B1 TCM (odd) ECC single error User/Privilege ESM 1.28
(correctable)
B1 TCM (odd) ECC double error User/Privilege Abort (CPU), ESM => nERROR 3.5
(non-correctable)
B1 TCM (odd) uncorrectable User/Privilege ESM => NMI 2.8
error (i.e. redundant address
decode)
B1 TCM (odd) address bus parity User/Privilege ESM => NMI 2.12
error
3) Flash with ECC INTEGRATED INTO CPU
ECC single error (correctable) User/Privilege ESM 1.6
ECC double error User/Privilege Abort (CPU), ESM => nERROR 3.7
(non-correctable)
Uncorrectable error (i.e. User/Privilege ESM => NMI 2.4
redundant address tag,
redundant syndrome compare,
address bus parity, etc.)
4) DMA transactions
External imprecise error on read User/Privilege ESM 1.5
(Illegal transaction with ok
response)
External imprecise error on write User/Privilege ESM 1.13
(Illegal transaction with ok
response)
(1) The Undefined Instruction TRAP is NOT detectable outside the CPU. The trap is taken only if the Code reaches the execute stage of
the CPU.
Copyright © 2010–2011, Texas Instruments Incorporated Reset / Abort Sources 37
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