Datasheet

TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
SPNS141F–AUGUST 2010– REVISED JULY 2011 www.ti.com
2.3.6 PBIST RAM Self Test
The PBIST (Programmable Built-In Self Test) architecture provides a run-time-programmable memory
BIST engine for varying levels of test coverage across the device’s embedded RAM memory. The PBIST
architecture consists of a small CPU with an instruction set targeted specifically towards testing RAM
memories. This CPU includes both control and instruction registers necessary to execute the individual
memory algorithms. In order to minimize test load overhead, once an algorithm is loaded into the
instruction registers, it can be run on multiple memories of different sizes or types. The memory
configuration information and test algorithm code is stored in an on-chip ROM. The PBIST RAM groups
implemented on this device are shown in the following table. More information about memory self test can
be found in the PBIST chapter of the device TRM.
Table 2-8. PBIST RAM Grouping
RAM Module Memory Type RGS Test Pattern (Algorithm)
Group /RDS
(1)
Triple Triple March Down 1A Pre- Map DTXN 2A PMOS
slow fast read 13N [HCLK/ charge column [HCLK/ open
read [ROM [HCLK/ VCLK
(2)
[HCLK/ [HCLK/ VCLK
(2)
[HCLK/
[ROM clock VCLK
(2)
cycles] VCLK
(2)
VCLK
(2)
cycles] VCLK
(2)
clock cycles] cycles] cycles] cycles] cycles]
cycles]
1 PBIST ROM 0/1 12290 4098
ROM
2 STC ROM 13/1 24578 8194
ROM
3 DCAN1 SP 1/0..2 12600 2637 2064 1914 5490 11544
4 DCAN2 SP 2/0..2 12600 2637 2064 1914 5490 11544
5 DCAN3 SP 3/0..2 6360 1341 1104 1146 2754 5016
6 ESRAM SP, multi-strobe 4/21..22 266320 52254 41120 33212 181260 409616
w/page mode
7 MibSPI SP 5/0..5 50160 10458 7968 6900 21924 52272
8 VIM SP 6/0 4200 879 688 638 1830 3848
9 MibADC 2P, sync write 7/0..1 8400 1758 1376 1276 3660 7696
async read
10 DMA 2P, sync write 8/0..5 18960 4410 3072 2772 6084 Not
async read Available
11 NHET 2P, sync write 9/0..11 25440 5940 4224 4008 8136 20064
async read
12 HET TU 2P, sync write 10/0..5 6480 1530 1152 1236 2052 4272
async read
13 RTP 2P, sync write 11/0..8 37800 8775 6048 5310 12150 34632
async read
14 FlexRay SP 12/0..7 175040 34872 27296 22608 108912 246336
15 ESRAM SP, multi-strobe 4/20 133160 26127 20560 16606 90630 204808
w/ page mode
SP = Single Port RAM; 2P = Two Port RAM
(1) RGS (RAM group select) and RDS (return data select) stand for an unique RAM select id. More information about the RGS and the
RDS can be found in the technical reference manual (TRM)
(2) The test clock for ESRAM, DMA and RTP is HCLK; the test clock for other modules is VCLK.
NOTE
• The March13N test algorithm is recommended for application testing.
• The maximum PBIST test execution speed is limited to 100MHz.
• The supply current while performing PBIST self test is different than the device operating
mode current. These values can be found in the I
cc
section of the device electrical
specifications.
16 Device Overview Copyright © 2010–2011, Texas Instruments Incorporated
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