Datasheet

TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
SPNS141F–AUGUST 2010– REVISED JULY 2011 www.ti.com
2.3.2 Flash Memory
The F035 (130nm Flash Process) Flash memory is a nonvolatile electrically erasable and programmable
memory. The Flash has a state machine for simplifying the program and erase functions.
This device’s 2M-Byte flash memory contains four 512K-Byte memory arrays (or banks) consisting of 22
total sectors. 1M-Byte versions of the device contain only the first two 512K-Byte banks (Bank 0 and Bank
1) and have a total of 14 sectors. The bank and sector configurations are shown in Flash Memory Banks
and Sectors . When in pipeline mode, the Flash operates with a system clock frequency of up to 160MHz
(versus a system clock in non-pipeline mode of up to 36MHz). The flash in pipeline mode is capable of
accessing 128 bits at a time and provides two 64-bit pipelined words to the CPU. The minimum size for an
erase operation is one sector. A single program operation can program either one 32-bit word or one
16-bit half word at a time.
Table 2-3. Flash Memory Banks and Sectors
MEMORY ARRAYS (OR
Sector NO. Segment Low Address High address
BANKS)
Bank 0: 512K Bytes
0 32K Bytes 0x0000_0000 0x0000_7FFF
1 32K Bytes 0x0000_8000 0x0000_FFFF
2 32K Bytes 0x0001_0000 0x0001_7FFF
3 8K Bytes 0x0001_8000 0x0001_9FFF
4 8K Bytes 0x0001_A000 0x0001_BFFF
BANK0 (512K Bytes)
5 16K Bytes 0x0001_C000 0x0001_FFFF
6 64K Bytes 0x0002_0000 0x0002_FFFF
7 64K Bytes 0x0003_0000 0x0003_FFFF
8 128K Bytes 0x0004_0000 0x0005_FFFF
9 128K Bytes 0x0006_0000 0x0007_FFFF
Bank 1: 512K Bytes
0 128K Bytes 0x0008_0000 0x0009_FFFF
1 128K Bytes 0x000A_0000 0x000B_FFFF
BANK1 (512K Bytes)
2 128K Bytes 0x000C_0000 0x000D_FFFF
3 128K Bytes 0x000E_0000 0x000F_FFFF
Bank 2: 512K Bytes
0 128K Bytes 0x0010_0000 0x0011_FFFF
1 128K Bytes 0x0012_0000 0x0013_FFFF
BANK2 (512K Bytes)
2 128K Bytes 0x0014_0000 0x0015_FFFF
3 128K Bytes 0x0016_0000 0x0017_FFFF
Bank 3: 512K Bytes
0 128K Bytes 0x0018_0000 0x0019_FFFF
1 128K Bytes 0x001A_0000 0x001B_FFFF
BANK3 (512k Bytes)
2 128K Bytes 0x001C_0000 0x001D_FFFF
3 128K Bytes 0x001E_0000 0x001F_FFFF
NOTE
• The external flash pump voltage (VccP) is required for all flash operations (program,
erase, and read). After a system reset, pipeline mode is disabled (FRDCNTL[2:0] is a
"000"). In other words, the device powers up and comes out of reset in non-pipeline
mode.
• The user must program proper ECC bits throughout the entire flash memory to avoid
ECC errors due to Cortex R4 speculative fetches if flash ECC is enabled.
• The flash on this device does not support EEPROM emulation.
12 Device Overview Copyright © 2010–2011, Texas Instruments Incorporated
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