Datasheet

www.ti.com
ELECTRICAL CHARACTERISTICS
PTV05010W
SLTS242A – FEBRUARY 2005 – REVISED OCTOBER 2005
operating at 25 ° C free-air temperature, V
I
= 5 V, V
O
= 3.3 V, C1 = 100 µ F, C2 = 10 µ F, C3 = 0 µ F, C4 = 0 µ F, and I
O
= I
O
max
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
O
Output current Natural convection airflow 0 8
(1)
A
V
I
Input voltage range Over I
O
load range 4.5 5.5 V
Set-point voltage tolerance 2%
(2)
Temperature variation – 40 ° C < T
A
< 85 ° C 0.5%
Line regulation Over V
I
range 5 mV
V
O
Load regulation Over I
O
range 5 mV
Total output variation Includes set-point, line, load, – 40 ° C ≤ T
A
≤ 85 ° C 3
(2)
%V
o
Adjust range Over V
I
range 0.8 3.6 V
R
SET
= 698 Ω , V
O
= 3.3 V 95%
R
SET
= 2.21 k Ω , V
O
= 2.5 V 93%
R
SET
= 5.49 k Ω , V
O
= 1.8 V 90%
η Efficiency I
O
= I
O
max
R
SET
= 8.87 k Ω , V
O
= 1.5 V 89%
R
SET
= 17.4 k Ω , V
O
= 1.2 V 87%
R
SET
= 36.5 k Ω , V
O
= 1 V 85%
Output voltage ripple (pk-pk) 20-MHz bandwidth 15 mV
PP
I
O
(trip) Overcurrent threshold Reset, followed by auto-recovery 12 A
1-A/ µ s load step, 50 to 100% I
O
max, C3 = 100 µ F
Transient response Recovery time 70 µ s
V
o
over/undershoot 100 mV
I
IL
Input low current Pin to GND – 0.13 mA
Track control (pin 9)
Control slew-rate limit C3 ≤ C3 (max) 1 V/ms
V
I
increasing 4.3 4.5
UVLO Undervoltage lockout V
V
I
decreasing 3.1 3.7
V
IH
Input high voltage V
I
– 0.5 Open
(3)
Referenced to GND V
Inhibit control (pin 12) V
IL
Input low voltage – 0.2 0.6
I
IL
Input low current Pin to GND 0.24 mA
I
I
(stby) Input standby current Inhibit (pin 7) to GND, Track (pin 5) open 5 mA
ƒ
S
Switching frequency Over V
I
and I
O
ranges 550 600 650 kHz
Nonceramic (C1) 100
(4)
External input capacitance µ F
Ceramic (C2) 10
(4)
Nonceramic 0 100
(5)
3300
(6)
Capacitance value µ F
External output capacitance (C3) Ceramic 0 300
Equivalent series resistance (nonceramic) 4
(7)
m Ω
Per Telcordia SR-332, 50% stress, T
A
= 40 ° C, ground
MTBF Reliability 5
10
6
Hr
benign
(1) See thermal derating curves for safe operating area (SOA), or consult factory for appropriate derating.
(2) The set-point voltage tolerance is affected by the tolerance and stability of R
SET
. The stated limit is unconditionally met if R
SET
has a
tolerance of 1%, with 100 ppm/ ° C or better temperature stability.
(3) This control pin is internally pulled up to the input voltage, V
I
. If this input is left open circuit, the module will operate when input power is
applied. A small low-leakage (< 100 nA) MOSFET is recommended for control. For further information, see the related application note.
(4) A 10- µ F high-frequency ceramic capacitor and 100- µ F electrolytic input capacitor are required for proper operation. The electrolytic
capacitor must be rated for 300 mArms minimum ripple current. See the Application Information for further guidance on capacitor
selection.
(5) An external output capacitor is not required for basic operation. Adding 100 µ F of distributed capacitance at the load improves the
transient response.
(6) This is the calculated maximum. The minimum ESR limitation often results in a lower value. When controlling the Track pin using a
voltage supervisor, C
O
(max) is reduced to 2200 µ F. See the Application Information for further guidance.
(7) This is the typical ESR for all the electrolytic (nonceramic) output capacitance. Use 7 m Ω as the minimum when using maximum-ESR
values to calculate.
Copyright © 2005, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s) :PTV05010W