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V 2=1.8V
O
V =5V
I
R2
5.49kW
ASIC
VCORE VCCIO
I 2
O
+
V 1=3.3V
O
R1
698 W
C1
+
C4
+
C6
+
C7
0.1µF
C3
C2
1,2
5,6
8
7
9
12
3,4
2,38
7
6 1 4
5
10,11
C5
PTV05010W
V
I
V
O
GND
GND
Inhibit
V Adj
O
Track
7
PTV05020W
V
I
V
O
GND
GND
Inhibit
V Adj
O
Track
V
CC
GND
SENSE
RESET
MR
CT
6
5
3
4
1
2
U3
TPS3808G33
U1
U2
Sense
PTV05010W
SLTS242A – FEBRUARY 2005 – REVISED OCTOBER 2005
prebias source. This condition must exist throughout the power-up sequence of the power system.
Figure 16. Application Circuit Demonstrating Prebias Start-Up
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