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FEATURESAPPLICATIONS

DESCRIPTION

PTMA40XXXX

Enable/Sync

Trim

I+

µF

(optional)

I−

TRIM(down)

(optional)

TRIM(up)

(optional)

47 µF

(optional)

O+

O−

UDG−06003

PTMA403033

PTMA402050

PTMA401120

SLTS259B–FEBRUARY2006–REVISEDMAY2007

10-W,36-Vto75-VINPUT,1500-VISOLATION,DC/DCCONVERTERS

•IntermediateBusArchitectures

•InputVoltage:36Vto75V

•Telecom,High-EndComputingPlatforms

•10-WTotalOutputPower

•PowerOverEthernetApplications

•OutputVoltages:3.3V,5V,and12V

•Multi-RailPowerSystems

•OutputVoltageTrim±10%

•UpTo87%Efficiency

•OvercurrentProtection

•InputUndervoltageLockout

•OutputOvervoltageProtection

•PositiveorNegativeLogic

EnableControlOption

•SynchronizationOption

•Space-Saving,IndustryStandardFootprint

(1.1inx1.0in)/(27.94mm×24.38mm)

•IndustryStandardPinout

•SurfaceMountPackage

•1500-VdcIsolation

•AgencyApprovals:

UL/IEC/CSA-C22.260950-1

ThePTMA40XXisaseriesof10-Wratedisolateddc/dcconverters,designedtooperatefromastandard-48-V

telecomcentralofficesupply.Housedinanindustrystandard1.1in×1.0in(27.94mm×24.38mm)package,

thisseriesofisolatedmodulesissettooneofthecommonintermediatebusvoltagesof3.3V,5V,or12V.

ThePTMA40XXseriesincludesmanyfeaturesexpectedofhigh-performancedc/dcconvertermodules.

Operationalfeaturesincludeaninputundervoltagelockout(UVLO)andadual-logicoutputenablecontrolor

synchronizationoption.Overcurrentprotectionensuressurvivalagainstloadfaults.

Typicalapplicationsincludedistributedpowerarchitecturesinbothtelecomandcomputingenvironments,power

overethernet,andparticularlycomplexdigitalsystemsrequiringmultiplepowersupplyrails.

TYPICALAPPLICATION

Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas

Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.

PRODUCTIONDATAinformationiscurrentasofpublicationdate.

ProductsconformtospecificationsperthetermsoftheTexas

Instrumentsstandardwarranty.Productionprocessingdoesnot

necessarilyincludetestingofallparameters.

Not Recommend for New Designs

Summary of content (30 pages)

PAGE 1
Not Recommend for New Designs PTMA403033 PTMA402050 PTMA401120 www.ti.com SLTS259B – FEBRUARY 2006 – REVISED MAY 2007 10-W, 36-V to 75-V INPUT, 1500-V ISOLATION, DC/DC CONVERTERS FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • • Input Voltage: 36 V to 75 V 10-W Total Output Power Output Voltages: 3.
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PTMA403033 PTMA402050 PTMA401120 Not Recommend for New Designs www.ti.com SLTS259B – FEBRUARY 2006 – REVISED MAY 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or see the TI website at www.ti.com.
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PTMA403033 PTMA402050 PTMA401120 Not Recommend for New Designs www.ti.com SLTS259B – FEBRUARY 2006 – REVISED MAY 2007 PTMA403033 ELECTRICAL CHARACTERISTICS TA = 25°C, VI = 48 V, VO = 3.3 V, CI = 0 µF, CO = 0 µF, and IO = IOmax (Unless otherwise stated) PARAMETER PO Output power PTMA403033 TEST CONDITIONS MIN Output current Over VI range ILIM Current Limit Threshold Shutdown, followed by autorecovery VI Input voltage range Over IO range 0.1 (1) 3 36 W (2) A 75 V A 48 ±2 UNIT 10 4.
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PTMA403033 PTMA402050 PTMA401120 Not Recommend for New Designs www.ti.com SLTS259B – FEBRUARY 2006 – REVISED MAY 2007 PTMA402050 ELECTRICAL CHARACTERISTICS TA = 25°C, VI = 48 V, VO = 5 V, CI = 0 µF, CO = 0 µF, and IO = IOmax (Unless otherwise stated) PARAMETER PO Output power PTMA402050 TEST CONDITIONS MIN Output current Over VI range ILIM Current Limit Threshold Shutdown, followed by autorecovery VI Input voltage range Over IO range 0.
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PTMA403033 PTMA402050 PTMA401120 Not Recommend for New Designs www.ti.com SLTS259B – FEBRUARY 2006 – REVISED MAY 2007 PTMA401120 ELECTRICAL CHARACTERISTICS TA = 25°C, VI = 48 V, VO = 12 V, CI = 0 µF, CO = 0 µF, and IO = IOmax (Unless otherwise stated) PARAMETER PO Output power PTMA401120 TEST CONDITIONS MIN Output current Over VI range ILIM Current Limit Threshold Shutdown, followed by autorecovery VI Input voltage range Over IO range 0.
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PTMA403033 PTMA402050 PTMA401120 Not Recommend for New Designs www.ti.com SLTS259B – FEBRUARY 2006 – REVISED MAY 2007 TERMINAL FUNCTIONS TERMINAL NAME Enable/Sync VI– (1) VI+ (1) VO+ DESCRIPTION NO. (1) 3 The Enable input is an open-base logic input that is referenced to VI–. Two ON/OFF enable options are available, positve logic and negative logic. Positive logic devices are enabled by applying a logic high voltage (Open) and are disabled by applying a logic low voltage (VI–).
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PTMA403033 PTMA402050 PTMA401120 Not Recommend for New Designs www.ti.com SLTS259B – FEBRUARY 2006 – REVISED MAY 2007 TYPICAL CHARACTERISTICS PTMA403033 Characteristic Data (VO = 3.3 V) (1) (2) EFFICIENCY vs OUTPUT CURRENT POWER DISSIPATION vs OUTPUT CURRENT 85 3.0 VIN = 48 V VIN = 36 V η Efficiency − % 75 VIN = 60 V 70 65 VIN = 75 V 60 VIN = 36 V 2.5 PD − Power Dissipation −W 80 2.0 1.5 VIN = 75 V 1.0 VIN = 48 V 0.5 VIN = 60 V 55 0 0 0.5 1.0 1.5 2.5 2.0 3.0 0 0.5 1.0 1.
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PTMA403033 PTMA402050 PTMA401120 Not Recommend for New Designs www.ti.com SLTS259B – FEBRUARY 2006 – REVISED MAY 2007 TYPICAL CHARACTERISTICS (continued) PTMA402050 Characteristic Data (VO = 5 V) (3) (4) EFFICIENCY vs OUTPUT CURRENT POWER DISSIPATION vs OUTPUT CURRENT 2.0 85 VIN = 48 V PD − Power Dissipation −W VIN = 36 V 80 η Efficiency − % 75 VIN = 60 V 70 65 1.6 VIN = 75 V 1.2 VIN = 60 V VIN = 75 V 60 VIN = 48 V 0.4 55 0 0.5 1.0 1.5 2.5 2.0 0 3.0 0.
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PTMA403033 PTMA402050 PTMA401120 Not Recommend for New Designs www.ti.com SLTS259B – FEBRUARY 2006 – REVISED MAY 2007 TYPICAL CHARACTERISTICS (continued) PTMA401120 Characteristic Data (VO = 12 V) (5) (6) EFFICIENCY vs OUTPUT CURRENT POWER DISSIPATION vs OUTPUT CURRENT 90 2 VIN = 36 V 85 VIN = 48 V VIN = 60 V 1.6 PD − Power Dissipation − W η − Efficiency − % VIN = 60 V 80 VIN = 75 V 75 70 VIN = 75 V 1.2 VIN = 48 V 0.8 65 VIN = 36 V 60 0 0.2 0.4 0.6 0.8 0.4 0 1 0.2 Figure 9.
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PTMA403033 PTMA402050 PTMA401120 Not Recommend for New Designs www.ti.com SLTS259B – FEBRUARY 2006 – REVISED MAY 2007 APPLICATION INFORMATION Operating Features and System Considerations for the PTMA40XX DC/DC Converters Primary-Secondary Isolation These converters incorporate electrical isolation between the input terminals (primary) and the output terminals (secondary). All converters are tested to a withstand voltage of 1500 Vdc.
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PTMA403033 PTMA402050 PTMA401120 Not Recommend for New Designs www.ti.com SLTS259B – FEBRUARY 2006 – REVISED MAY 2007 APPLICATION INFORMATION (continued) VIN (10 V/div) VOUT (1 V/div) IIN (100 mA/div) t − Time − 20 ms/div Figure 13. Power-up Waveforms Output Voltage Trim Adjustment An external resistor is required to increase or decrease the output voltage set point of the module by ± 10 %.
PAGE 12
PTMA403033 PTMA402050 PTMA401120 Not Recommend for New Designs www.ti.com SLTS259B – FEBRUARY 2006 – REVISED MAY 2007 For other output voltages, the value of the required trim resistor may be calculated using Equation 1 to adjust the voltage up or Equation 2 to adjust the voltage down. RO V R R TRIM(up) + * RP (kW) ǒVO * VSETǓ (1) RO ǒVO * VRǓ R TRIM(dwn) + * R P (kW) ǒVSET * VOǓ (2) Table 2 gives the required RTRIM equation constants for the converter model selected.
PAGE 13
Not Recommend for New Designs www.ti.com PTMA403033 PTMA402050 PTMA401120 SLTS259B – FEBRUARY 2006 – REVISED MAY 2007 Enable Control Schematic VI + 1 VI + 3 ENABLE/SYNC On/Off Control 2 VI − VI − Figure 15. Typical On/Off Enable Control Circuit On/Off Enable Turn-On Time Once enabled, the converter executes a soft-start power up. The converter exibits a short delay of approximately 100 µs, measured from the transition of the enable signal to the instance the VO Bus output begins to rise.
PAGE 14
PTMA403033 PTMA402050 PTMA401120 Not Recommend for New Designs www.ti.com SLTS259B – FEBRUARY 2006 – REVISED MAY 2007 Synchronization The Synchronization option allows multiple power modules to be synchronized to a common frequency. Driving the Sync pin (pin 3) with an external clock set to the desired frequency, synchronizes all connected modules to that frequency. Modules with the synchronization option have a reduced free-running switching frequency of 215 kHz typical.
PAGE 15
Not Recommend for New Designs www.ti.com PTMA403033 PTMA402050 PTMA401120 SLTS259B – FEBRUARY 2006 – REVISED MAY 2007 MECHANICALS (continued) Tray © This Document and the information contained herein is confidential and proprietary to Texas Instrumants, and may not be reproduced or used for any purpose without the expressed written permission of Texas Instruments.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 2-Oct-2014 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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