Datasheet

ELECTRICAL CHARACTERISTICS
PTH12060W/L
www.ti.com .................................................................................................................................................... SLTS217H – MAY 2003 – REVISED DECEMBER 2008
T
A
= 25C; V
I
= 12 V; V
O
= 3.3 V; C
I
= 560 µ F, C
O
= 0 µ F, and I
O
= I
O
max (unless otherwise stated)
PTH12060W UNIT
PARAMETER TEST CONDITIONS
MIN TYP MAX
T
A
= 60 ° C, 200 LFM airflow 0 10
(1)
A
I
O
Output current Over Δ V
adj
range
T
A
= 25 ° C, natural convection 10
(1)
A
V
I
Input voltage range Over I
O
range 10.8 13.2 V
V
O tol
Set-point voltage tolerance ± 2
(2)
%V
O
Δ Reg
temp
Temperature variation – 40 ° C < T
A
< 85 ° C ± 0.5 %V
O
Δ Reg
line
Line regulation Over V
in
range ± 10 mV
Δ Reg
load
Load regulation Over I
o
range ± 12 mV
Δ Reg
tot
Total output variation Includes set-point, line, load, – 40 ° C ≤ T
A
≤ 85 ° C ± 3 %V
O
Δ V
adj
Output voltage adjust range Over V
in
range 1.2 5.5 V
R
SET
= 280 Ω , V
O
= 5.0 V 94%
R
SET
= 2.0 k Ω , V
O
= 3.3 V 92%
R
SET
= 4.32 k Ω , V
O
= 2.5 V 90%
η Efficiency I
O
= 8 A
R
SET
= 11.5 k Ω , V
O
= 1.8 V 87%
R
SET
= 24.3 k Ω , V
O
= 1.5 V 85%
R
SET
= open circuit, V
O
= 1.2 V 83%
V
O
≤ 2.5 V 25
(3)
mV
PP
20-MHz bandwidth,
V
O
ripple (peak-to-peak)
with C
O
2 = 10 µ F ceramic
V
O
> 2.5 V 1
(3)
%V
O
I
O
trip Overcurrent threshold Reset, followed by auto-recovery 20 A
t
tr
1 A/ µ s load step, 50 to Recovery time 70 µ S
Transient response 100% I
o
max,
V
o
over/undershoot 100 mV
Δ V
tr
C
O
1 = 330 µ F
V
O
adj Margin up/down adjust ± 5%
I
IL
margin Margin input current (pins 9/10) Pin to GND – 8
(4)
µ A
I
IL
track Track input current (pin 8) Pin to GND – 0.11
(5)
mA
dV
track
/dt Track slew rate capability C
O
≤ C
O
(max) 1 V/ms
V
I
increasing 9.5 10.4
UVLO Undervoltage lockout V
V
I
decreasing 8.8 9
V
IH
Input high voltage, Referenced to GND Open
(5)
V
V
IL
Inhibit Control (pin 3) Input low voltage, Referenced to GND – 0.2 0.5
I
IL
Input low current, Pin 3 to GND 0.24 mA
I
I
Input standby current Inhibit (pin 3) to GND, Track (pin 8) open 10 mA
f
s
Switching frequency Over V
I
and I
O
ranges 300 350 400 kHz
C
I
External input capacitance 560
(6)
µ F
Nonceramic 0 330
(7)
5500
(8)
Capacitance value µ F
C
O
External output capacitance Ceramic 0 300
Equivalent series resistance (nonceramic) 4
(9)
m Ω
6.4
MTBF Reliability Per Bellcore TR-332, 50% stress, T
A
= 40 ° C, ground benign
10
6
Hr
(1) See SOA curves or consult factory for appropriate derating.
(2) The set-point voltage tolerance is affected by the tolerance and stability of R
SET
. The stated limit is unconditionally met if R
SET
has a
tolerance of 1% with 100 ppm/ ° C or better temperature stability.
(3) The peak-to-peak output ripple voltage is measured with an external 10- µ F ceramic capacitor. See the standard application schematic.
(4) A small, low leakage ( < 100 nA) MOSFET is recommended to control this pin. The open-circuit voltage is less than 1 Vdc.
(5) This control pin has an internal pull-up to the input voltage V
I
. If it is left open-circuit, the module operates when input power is applied.
A small, low-leakage ( < 100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control. Do not place an
external pull-up on this pin. For further information, see the related application information section.
(6) A 560 µ F input capacitor are required for proper operation. The electrolytic capacitor must be rated for a minimum of 1050 mA rms of
ripple current.
(7) An external output capacitor is not required for basic operation. Adding 330 µ F of distributed capacitance at the load improves the
transient response.
(8) This is the calculated maximum. The minimum ESR limitation oftens result in a lower value. When controlling the Track pin using a
voltage supervisor, C
O
(max) is reduced to 2200 µ F. See the application notes for further guidance.
(9) This is the typical ESR for all the electrolytic (nonceramic) output capacitance. Use 7 m Ω as the minimum when using max-ESR values
to calculate.
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