Datasheet
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ELECTRICAL CHARACTERISTICS
PTH12050W/L
SLTS214H – MAY 2003 – REVISED OCTOBER 2007
T
A
= 25 ° C; V
I
= 12 V; V
O
= 1.8 V; C1 = 100 µF, C2 = 10 µF, C3 = 0 µF, and I
O
= I
O(max)
(unless otherwise stated)
PARAMETER TEST CONDITIONS PTH12050L UNIT
MIN TYP MAX
85 ° C, 400 LFM airflow 0 6
(1)
A
I
O
Output current Over Δ V
adj
range
60 ° C, natural convection 6
(1)
A
V
I
Input voltage range Over I
O
range 10.8 13.2 V
V
Otol
Set-point voltage tolerance ± 2
(2)
%V
o
Δ Reg
temp
Temperature variation – 40 ° C <T
A
< 85 ° C ± 0.5 %V
o
Δ Reg
line
Line regulation Over V
I
range ± 5 mV
Δ Reg
load
Load regulation Over I
O
range ± 5 mV
Δ Reg
tot
Total output variation Includes set-point, line, load, – 40 ° C ≤ T
A
≤ 85 ° C ± 3
(2)
%V
o
Δ Reg
adj
Output voltage adjust range Over V
I
range 0.8 1.8 V
R
SET
= 130 Ω , V
O
= 1.8 V 88%
R
SET
= 3.57 k Ω , V
O
= 1.5 V 87%
η Efficiency I
O
= 5 A R
SET
= 12.1 k Ω , V
O
= 1.2 V 85%
R
SET
= 32.4 k Ω , V
O
= 1 V 83%
R
SET
= open circuit, V
O
= 0.8 V 81%
V
O
> 1 V 30
V
r
V
o
ripple (peak-to-peak) 20-MHz bandwidth mVpp
V
O
≤ 1 V 20
I
o
trip Overcurrent threshold Reset, followed by auto-recovery 14 A
t
tr
1 A/µs load step, Recovery time 70 µs
Transient response 50 to 100% I
O(max)
,
Δ V
tr
V
O
over/undershoot 100 mV
C
3
= 100 µF
I
IL
track Track input current (pin 2) Pin to GND – 0.13
(3)
mA
dV
track
/dt Track slew rate capability C
O
≤ C
O(max)
1 V/ms
V
I
increasing 9.5 10.4
UVLO Undervoltage lockout V
V
I
decreasing 8.8 9
V
IH
Input high voltage, Referenced to GND Open
(3)
V
V
IL
Inhibit control (pin 4) Input low voltage, Referenced to GND – 0.2 0.5
I
IL
Input low current, Pin 4 to GND 0.24 mA
I
I
Input standby current Inhibit (pin 4) to GND, Track (pin 2) open 10 mA
f
s
Switching frequency Over V
I
and I
O
ranges 200 250 300 kHz
External input capacitance, C1 100
(4)
µF
Nonceramic 0 100
(5)
3300
(6)
Capacitance value µF
External output capacitance, C3 Ceramic 0 300
Equivalent series resistance (nonceramic) 4
(7)
5.9
MTBF Reliability Per Bellcore TR-332 50% stress, T
A
= 40 ° C, ground benign
10
6
Hr
(1) See the Temperature Derating (SOA) curves in the Typical Characteristics section for appropriate derating.
(2) The set-point voltage tolerance is affected by the tolerance and stability of R
SET
. The stated limit is unconditionally met if R
SET
has a
tolerance of 1% with 100 ppm/ ° C or better temperature stability.
(3) This control pin has an internal pull-up to the input voltage V
I
(7.5 V for pin 2). If it is left open-circuit, the module operates when input
power is applied. A small, low-leakage (<100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control. Do
not place an external pull-up on this pin. For further information, see the related application note.
(4) A 100 µF electrolytic input capacitor is required for proper operation. The electrolytic capacitor must be rated for a minimum of 750 mA
rms of ripple current. An additional 10 µF ceramic capacitor is required for output voltages 3.3 V and higher. For further information, see
the related application information on capacitor selection.
(5) An external output capacitor is not required for basic operation. Adding 100 µF of distributed capacitance at the load improves the
transient response.
(6) This is the calculated maximum. The minimum ESR limitation oftens result in a lower value. When controlling the Track pin using a
voltage supervisor, C
O
(max) is reduced to 2200 μ F. See the application notes for further guidance.
(7) This is the typical ESR for all the electrolytic (nonceramic) output capacitance. Use 7 m Ω as the minimum when using max-ESR values
to calculate.
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