Datasheet
ELECTRICAL CHARACTERISTICS
PTH12040W
www.ti.com
............................................................................................................................................... SLTS237G – DECEMBER 2004 – REVISED MARCH 2009
T
A
= 25 ° C, V
I
= 12 V, V
O
= 3.3 V, C
I
= 1000 µ F, C
O
= 660 µ F, and I
O
= I
O
max (unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
O
Output current 60 ° C, 200 LFM airflow 0 50
(1)
A
V
I
Input voltage range Over I
O
range 8
(2)
14 V
V
O
tol Set-point voltage tolerance ± 2
(3)
%V
O
Δ Reg
temp
Temperature variation – 40 ° C < T
A
< 85 ° C ± 0.5 %V
O
Δ Reg
line
Line regulation Over V
I
range ± 5 mV
Δ Reg
load
Load regulation Over I
O
range ± 5 mV
Δ Reg
tot
Total output variation Includes set-point, line, load, – 40 ° C ≤ T
A
≤ 85 ° C ± 3
(3)
%V
O
Δ Reg
adj
Output adjust range 0.8 5.5
(2)
V
R
SET
= 205 Ω , V
O
= 5.0 V 96%
R
SET
= 1.5 k Ω , V
O
= 3.3 V 95%
R
SET
= 3.01 k Ω , V
O
= 2.5 V 93%
R
SET
= 4.99 k Ω , V
O
= 2.0 V 92%
η Efficiency I
O
= 35 A R
SET
= 6.34 k Ω , V
O
= 1.8 V 91%
R
SET
= 9.76 k Ω , V
O
= 1.5 V 90%
R
SET
= 18.2 k Ω , V
O
= 1.2 V 88%
R
SET
= 38.3 k Ω , V
O
= 1.0 V 86%
R
SET
= open circuit, V
O
= 0.8 V 82%
V
R
V
O
ripple (pk-pk) 20 MHz bandwidth All voltages 15 mVpp
I
O
trip Overcurrent threshold Reset, followed by auto-recovery 95 A
Transient response 1 A/ µ s load step, 50 to 100% I
O
max, C
O
= 660 µ F
t
rr
Recovery time 70 µ Sec
Δ V
tr
V
O
over/undershoot 150 mV
V
O
adj Margin up/down adjust With Margin up/down control ± 5%
I
IL
margin Margin input current Pin to GND – 8
(4)
µ A
I
IL
track Track input current (pin 18) Pin to GND – 0.10
(5)
mA
dV
track
/dt Track slew rate capability |V
TRACK
– V
O
| ≤ 50 mV and V
TRACK
< V
O
(nom) 1 V/ms
UVLO Undervoltage lockout Pin 8 open On-threshold 7.5
(6)
V
Hysterisis 1
(6)
Inhibit control (pin 7) Referenced to GND
V
IH
Input high voltage 2.5 Open
(7)
V
V
IL
Input low voltage – 0.2 0.5
I
IL
inhibit Input low current Pin to GND 0.5 mA
I
I
inh Input standby current Inhibit (pin 7) to GND 35 mA
f
s
Switching frequency Over V
I
and I
O
ranges 0.9 1.05 1.2 MHz
C
I
External input capacitance 560
(8)
1000 µ F
(1) See SOA curves or consult factory for appropriate derating.
(2) When the set-point voltage is adjusted higher than 3.6 V, a 10-V minimum input voltage is recommended.
(3) The set-point voltage tolerance is affected by the tolerance of R
SET
. The stated limit is unconditionally met if R
SET
has a tolerance of 1%
with 100 ppm/ ° C or better temperature stability.
(4) A small, low-leakage ( < 100 nA) MOSFET is recommended to control this pin. The open-circuit voltage is less than 1 Vdc.
(5) This control pin has an internal pull-up to 6.7 V. If left open-circuit, the module operates when input power is applied. A small, low
leakage ( < 100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control. See the Application Information
section for further guidance.
(6) Default voltages may be adjusted using the UVLO Prog control input. See the Application Information section for further guidance.
(7) This control pin has an internal pull-up to 5 V nominal. If it is left open-circuit, the module operates when input power is applied. A small,
low-leakage ( < 100 nA) MOSFET is recommended for control. Do not place an external pull-up on this pin. For further information, see
the related application note.
(8) A minimum capacitance of 560- µ F is required at the input for proper operation. For best results, 1000 µ F is recommended. The
capacitance must be rated for a minimum of 300 mArms of ripple current.
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