Datasheet

Prebias Startup Capability
UVLO
Threshold
V (5V/Div)
I
V (1V/Div)
O
HORIZTAL SCALE:5ms/Div
StartupPeriod
HORIZTAL SCALE:10ms/Div
V 1(1V/Div)
O
V (1V/Div)
O
2
I 2(5 A/Div)
O
PTH12040W
www.ti.com ............................................................................................................................................... SLTS237G – DECEMBER 2004 – REVISED MARCH 2009
The capability to start up into an output prebias condition is available to all the 12-V input series of PTH/PTV
power modules. A prebias startup condition occurs as a result of an external voltage being present at the output
of a power module prior to its output becoming active. This often occurs in complex digital systems when current
from another power source is backfed through a dual-supply logic component, such as an FPGA or ASIC.
Another path might be via clamp diodes, sometimes used as part of a dual-supply power-up sequencing
arrangement. A prebias can cause problems with power modules that incorporate synchronous rectifiers. This is
because under most operating conditions, such modules can sink as well as source output current. The 12-V
input PTH modules all incorporate synchronous rectifiers, but do not sink current during startup, or whenever the
Inhibit pin is held low. Start up includes an initial delay (approximately 8 – 15 ms), followed by the rise of the
output voltage under the control of the module ’ s internal soft-start mechanism; see Figure 18 .
Conditions for PreBias Holdoff
For the module to allow an output prebias voltage to exist (and not sink current), certain conditions must be
maintained. The module holds off a prebias voltage when the Inhibit pin is held low, and whenver the output is
allowed to rise under soft-start control. Power up under soft-start control occurs upon the removal of the ground
signal to the Inhibit pin (with input voltage applied), or when input power is applied with Auto-Track disabled
[1]
. To
further ensure that the regulator doesn ’ t sink output current, (even with a ground signal applied to its Inhibit), the
input voltage must always be greater than the applied prebias source. This condition must exist throughout the
power-up sequence.
The soft-start period is complete when the output begins rising above the prebias voltage. Once it is complete
the module functions as normal, and sinks current if a voltage higher than the nominal regulation value is applied
to its output.
Note: If a prebias condition is not present, the soft-start period is complete when the output voltage has risen
to either the set-point voltage, or the voltage applied at the module ’ s Track control pin, whichever is lowest.
Demonstration Circuit
Figure 19 shows the startup waveforms for the demonstration circuit shown in Figure 20 . The initial rise in V
O
2 is
the prebias voltage, which is passed from the VCCIO to the VCORE voltage rail through the ASIC. Note that the
output current from the PTH12010L module (I
O
2) is negligible until its output voltage rises above the applied
pre-bias.
Figure 18. PTH12020W Startup Figure 19. Pre-Bias Startup Waveforms
Copyright © 2004 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): PTH12040W