Datasheet

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6-A, 12-V Input Non-Isolated
Wide-Output Adjust Power Module
SLTS202E– MAY 2003 – REVISED NOVENBER 2007
PTH12000L — 12-V Input
Electrical Specifications Unless otherwise stated, T
a
=25 °C, V
in
=12 V, V
o
=1.8 V, C
1
=100 μF, C
2
=0 μF, C
3
=0 μF, and I
o
=I
o
max
PTH12000L
Characteristics Symbols Conditions Min Typ Max Units
Output Current I
o
Over ΔV
adj
range, T
a
=85 °C, natural convection 0 — 6 A
Input Voltage Range V
in
Over I
o
range 10.8 — 13.2 V
Set-Point Voltage Tolerance V
o
tol — — ±2
(1)
%V
o
Temperature Variation ΔReg
temp
–40 °C <T
a
< +85 °C — ±0.5 — %V
o
Line Regulation ΔReg
line
Over V
in
range — ±5 — mV
Load Regulation ΔReg
load
Over I
o
range — ±5 — mV
Total Output Variation ΔReg
tot
Includes set-point, line, load,
——±3
(1)
%V
o
–40 °C ≤ T
a
≤ +85 °C
Ouput Voltage Adjust Range ΔV
adj
Over V
in
range 0.8 — 1.8 V
Efficiency η V
in
=12 V, I
o
=4 A R
SET
= 130 Ω V
o
= 1.8 V — 87 —
R
SET
= 3.57 kΩ V
o
= 1.5 V — 86 —
R
SET
= 12.1 kΩ V
o
= 1.2 V — 85 — %
R
SET
= 32.4 kΩ V
o
= 1.0 V — 82 —
R
SET
= Open cctV
o
= 0.8 V — 79 —
V
o
Ripple (pk-pk) V
r
20 MHz bandwidth, I
o
=4 A V
o
> 1.2 V — 25
(2)
—
mVpp
C
3
=10 μF ceramic V
o
≤ 1.2 V — 20
(2)
—
Transient Response 1 A/μs load step, 50 to 100 % I
o
max,
V
o
=1.8 V, C
2
=100 μF
t
tr
Recovery time — 70 — μSec
ΔV
tr
V
o
over/undershoot — 100 — mV
Over-Current Threshold I
o
trip Reset followed by auto-recovery — 12 — A
Under-Voltage Lockout UVLO V
in
increasing — — 10.4
V
V
in
decreasing 8.8 — —
Inhibit Control (pin 3) Referenced to GND
Input High Voltage V
IH
V
in
–0.5 — Open
(3)
V
Input Low Voltage
V
IL
–0.2 — 0.5
Input Low Current
I
IL Pin 3 to GND — –240 — μA
Standby Input Current I
in
standby pins 1 & 3 connected — 1 — mA
Switching Frequency ƒ
s
Over V
in
and I
o
ranges 200 250 300 kHz
External Input Capacitance C
in
100
(4)
——μF
External Output Capacitance C
out
Capacitance value non-ceramic 0 100
(5)
3,300
(6)
μF
ceramic 0 — 300
Equiv. series resistance (non-ceramic) 4
(7)
——mΩ
Reliability MTBF Per Bellcore TR-332
9.4 — — 10
6
Hrs
50 % stress, T
a
=40 °C, ground benign
Notes: (1) The set-point voltage tolerance is affected by the tolerance and stability ofR
SET
. The stated limit is unconditionally met if R
SET
has a tolerance of 1%
with 100 ppm/°C or better temperature stability.
(2) The pk-pk output ripple voltage is measured with an external 10 μF ceramic capacitor. See the standard application schematic.
(3) The Inhibit control (pin 3) has an internal pull-up to Vin, and if left open-circuit the module will operate when input power is applied. A small low-
leakage (<100 nA) MOSFET is recommended to control this input. See application notes for more information.
(4) The regulator requires a minimum of 100 μF input capacitor with a minimum 750 mArms ripple current rating. For further information, consult the
related application note on Capacitor Recommendations.
(5) An external output capacitor is not required for basic operation. Adding 100 μF of distributed capacitance at the load will improve the transient response.
(6) This is the calculated maximum. The minimum ESR limitation will often result in a lower value. Consult the application notes for further guidance.
(7) This is the typical ESR for all the electrolytic (non-ceramic) output capacitance. Use 7 m
Ω as the minimum when using max-ESR values to calculate.