Datasheet

Application Notes
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Pre-Bias Startup Capability
The capability to start up into an output pre-bias condi-
tion is now a feature of the PTH12000 series of modules.
(Note: This is a feature enhancement for the the W-suffix
version; see note 1).
A pre-bias startup condition occurs as a result of an external
voltage being present at the output of a power module prior
to its output becoming active. This often occurs in com-
plex digital systems when current from another power
source is backfed through a dual-supply logic component,
such as an FPGA or ASIC. Another path might be via
clamp diodes, sometimes used as part of a dual-supply
power-up sequencing arrangement. A prebias can cause
problems with power modules that incorporate synchro-
nous rectifiers. This is because under most operating
conditions, such modules can sink as well as source output
current. The PTH12000x series of modules incorporate
synchronous rectifiers, but will not sink current during
startup, or whenever the Inhibit pin is held low. Startup
includes an initial delay (approx. 8 - 15 ms), followed by
the rise of the output voltage under the control of the
module’s internal soft-start mechanism; see Figure 3-1.
Conditions for Pre-Bias Holdoff
In order for the module to allow an output pre-bias voltage
to exist (and not sink current), certain conditions must be
maintained. The module holds off a pre-bias voltage when
the Inhibit pin is held low, and whenver the output is
allowed to rise under soft-start control. Power up under
soft-start control occurs upon the removal of the ground
signal to the Inhibit pin (with input voltage applied), or
when input power is applied. To further ensure that the
regulator doesn’t sink output current, (even with a ground
signal applied to its Inhibit), the input voltage must always
be greater than the applied pre-bias source. This condi-
tion must exist throughout the power-up sequence
3
.
The soft-start period is complete when the output begins
rising above the pre-bias voltage. Once it is complete the
module functions as normal, and will sink current if a
voltage higher than the nominal regulation value is applied
to its output.
Note: If a pre-bias condition is not present, the soft-start period
will be complete when the output voltage has risen to either
the set-point voltage.
Demonstration Circuit
The circuit shown in Figure 3-4 is a demonstrates the
pre-bias startup feature. Figure 3-5 shows the startup
waveforms. The initial rise in Vo
2
is the pre-bias volt-
age, which is passed from the VCCIO to the VCORE
voltage rail through the ASIC. Note that the output cur-
rent from the PTH12000L module (Io
2
) is negligible
until its output voltage rises above the applied pre-bias.
Figure 3–4; Application Circuit Demonstrating Pre-Bias Startup
Vo
2
= 1.8 V
V
IN
= 12 V
R
2
130
ASIC
VCORE
VCCIO
Io
2
+
Vo
1
= 3.3 V
R
1
2k
C
2
330 µF
+
C
1
330 µF
+
PTH12020W
7
10
4
5
62
3
98
Track
V
IN
V
O
GNDInhibit
1
Up Dn Sense
Adjust
C
3
330 µF
+
TL7702B
V
CC
GND
SENSE
RESIN
REF
CT
RESET
RESET
8
7
2
1
3
5
6
4
C
6
0.68 µF
C
4
330 µF
+
R
3
11k0
R
4
100k
C
5
0.1 µF
R
5
10k0
PTH12000L
14
52
3
V
IN
V
O
GNDInh Adj
PTH12000 Series