Datasheet
ELECTRICAL CHARACTERISTICS
PTH08T255W
SLTS290 – NOVEMBER 2008 ...........................................................................................................................................................................................
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PTH08T255W
T
A
= 25 ° C, V
I
= 12 V, V
O
= 3.3 V, C
I
= 1000 µ F, C
O
= 1000 µ F, and I
O
= I
O
max (unless otherwise stated)
PARAMETER TEST CONDITIONS PTH08T255W UNIT
MIN TYP MAX
25 ° C, natural convection 0 40
I
O
Output current Over V
O
range A
60 ° C, 200 LFM 0 40
V
I
Input voltage range Over I
O
and V
O
range 8.0 14 V
V
OADJ
Output voltage adjust range Over I
O
range 3.0 5.25 V
Set-point voltage tolerance ± 0.5 ± 1
(1)
%V
o
Temperature variation – 40 ° C < T
A
< 85 ° C ± 0.3 %V
o
V
O
Line regulaltion Over V
I
range ± 5 mV
Load regulation Over I
O
range ± 5 mV
Total output variation Includes set-point, line, load, – 40 ° C ≤ T
A
≤ 85 ° C ± 1.5
(1)
%V
o
R
SET
= 1.36 k Ω , V
O
= 5.0 V 95%
η Efficiency I
O
= 30 A
R
SET
= 34.5 k Ω , V
O
= 3.3 V 94%
V
O
Ripple (peak-to-peak) 20-MHz bandwidth 20 mV
PP
I
LIM
Overcurrent threshold Reset, followed by auto-recovery 80 A
t
tr
Recovery time 200 µ s
w/o TurboTrans
C
O
= 1000 µ F, TypeC
Δ V
tr
V
O
over/undershoot 135 mV
2.5 A/ µ s load step
Transient response
50 to 100% I
O
max
t
trTT
w/ TurboTrans Recovery time 400 µ s
C
O
= 5000 µ F, TypeC
mV
Δ V
trTT
V
O
over/undershoot 35
R
TT
= short
I
IL
Track input current (pin 20) Pin to GND – 130
(2)
µ A
dV
track
/dt Track slew rate capability C
O
≤ C
O
(max) 1 V/ms
V
I
increasing, R
UVLO
= OPEN 7.2 8.0
Adjustable Under-voltage lockout
UVLO
ADJ
V
I
decreasing, R
UVLO
= OPEN 6.7 V
(pin 21)
Hysteresis 0.5
Input high voltage (V
IH
) Open
(3)
V
Inhibit control (pin 21) Input low voltage (V
IL
) -0.2 0.6
Input low current (I
IL
), Pin 21 to GND -125 µ A
I
in
Input standby current Inhibit (pin 21) to GND, Track (pin 20) open 35 mA
f
s
Switching frequency Over V
I
and I
O
ranges, SmartSync (pin 22) to GND 600
(4)
kHz
f
SYNC
Synchronization frequency applied to pin 22 240
(4)
400
(4)
kHz
V
SYNCH
SYNC High-Level Input Voltage 2.0 5.5 V
Synchronization (SYNC)
control (pin 22)
V
SYNCL
SYNC Low-Level Input Voltage 0.8 V
t
SYNC
SYNC Minimum Pulse Width 200 nSec
Nonceramic 1000
(5)
C
I
External input capacitance µ F
Ceramic 22
(1) The set-point voltage tolerance is affected by the tolerance and stability of R
SET
. The stated limit is unconditionally met if R
SET
has a
tolerance of 1% with 100 ppm/C or better temperature stability.
(2) A low-leakage ( < 100 nA), open-drain device, such as MOSFET or voltage supervisor IC, is recommended to control pin 20. When using
this feature, a 100k Ω pull-up resistor to V
I
is required. If unused, this pin must be directly connected to V
I
. See the Auto-Track section of
the datasheet for more information.
(3) Do not place an external pull-up on this pin. If it is left open-circuit, the module operates when input power is applied. A small,
low-leakage ( < 100 nA) MOSFET is recommended for control. For additional information, see the On/Off Inhibit section of the datasheet.
(4) The PTH08T255W is a two-phase power module. Each phase switches at 300kHz typical, 180 ° out of phase from one another. The
over-all switching frequency is 600 kHz typical. SmartSync controls the frequency of an individual phase.
(5) A 1000 µ F electrolytic input capacitor is required for proper operation. The input capacitor must be rated for a minimum of 750 mA rms
of ripple current.
4 Copyright © 2008, Texas Instruments Incorporated
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