Datasheet

R
UVLO
=
70.74-V
THD
V -4.26
THD
k W
Inhibit/
UVLO Prog
GND
PTH08T230W
3
2
10
+
GND
R
UVLO
V
I
V
I
C
I
PTH08T230W, PTH08T231W
www.ti.com SLTS265L –NOVEMBER 2005– REVISED AUGUST 2011
UNDERVOLTAGE LOCKOUT (UVLO)
The PTH08T230/231W power modules incorporate an input undervoltage lockout (UVLO). The UVLO feature
prevents the operation of the module until there is sufficient input voltage to produce a valid output voltage. This
enables the module to provide a clean, monotonic powerup for the load circuit, and also limits the magnitude of
current drawn from the regulator’s input source during the power-up sequence.
The UVLO characteristic is defined by the ON threshold (V
THD
) voltage. Below the ON threshold, the Inhibit
control is overridden, and the module does not produce an output. The hysteresis voltage, which is the difference
between the ON and OFF threshold voltages, is set at 500 mV. The hysteresis prevents start-up oscillations,
which can occur if the input voltage droops slightly when the module begins drawing current from the input
source.
The UVLO feature of the PTH08T230/231W module allows for limited adjustment of the ON threshold voltage.
The adjustment is made via the Inhibit/UVLO control pin (pin 10) using a single resistor (see Figure 19). When
pin 10 is left open circuit, the ON threshold voltage is internally set to its default value, which is 4.3 V. The ON
threshold might need to be raised if the module is powered from a tightly regulated 12-V bus. Adjusting the
threshold prevents the module from operating if the input bus fails to completely rise to its specified regulation
voltage.
Threshold Adjust
Equation 5 determines the value of R
UVLO
required to adjust V
THD
to a new value. The default value is 4.3 V, and
it may be adjusted, but only to a higher value.
(5)
Calculated Values
Table 7 shows a chart of standard resistor values for R
UVLO
for different values of the ON threshold (V
THD
)
voltage.
Table 7. Standard R
UVLO
values for Various V
THD
values
V
THD
(V) 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0
R
UVLO
(kΩ) 88.7 52.3 37.4 28.7 23.2 19.6 16.9 14.7 13.0 11.8 10.5 9.76 8.87
Figure 19. UVLO Implementation
Copyright © 2005–2011, Texas Instruments Incorporated 23