Datasheet

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ELECTRICAL CHARACTERISTICS
PTH04070W
SLTS227B – SEPTEMBER 2004 – REVISED OCTOBER 2007
at 25C free-air temperature, V
I
= 5 V, V
O
= 3.3 V, I
O
= I
O
(Max), C1 = 47 μ F, C2 = 47 μ F (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
O
Output current T
A
= 85 ° C, natural convection airflow 0 3 A
V
I
Input voltage range Over I
O
range 3 5.5 V
V
O(tol)
Set-point voltage tolerance T
A
= 25 ° C ± 2
(1)
%V
O
Temperature variation -40 ≤ T
A
≤ +85 ° C ± 0.5 %V
O
Line regulation Over V
I
range ± 1 mV
Load regulation Over I
O
range ± 5 mV
Includes set-point, line, load,
Total output voltage variation ± 3
(1)
%V
O
– 40 ≤ T
A
≤ +85 ° C
V
I
≥ 4.5 V 0.9 3.6
V
O(adj)
Output voltage adjust range V
V
I
< 4.5 V 0.9 V
I
– 1.1
(2)
T
A
= 25 ° C, I
O
= 2 A
R
SET
= 475 Ω , V
O
= 3.3 V
(2)
92%
R
SET
= 2.32 k Ω , V
O
= 2.5 V V
(2)
90%
R
SET
= 4.87 k Ω , V
O
= 2 V 88%
η Efficiency
R
SET
= 6.65 k Ω , V
O
= 1.8 V 87%
R
SET
= 11.5 k Ω , V
O
= 1.5 V 85%
R
SET
= 26.1 k Ω , V
O
= 1.2 V 82%
R
SET
= 84.5 k Ω , V
O
= 1 V 80%
Output voltage ripple 20 MHz bandwith 10 mV
PP
I
O(trip)
Overcurrent threshold Reset, followed by autorecovery 7 A
C3 = 47 μ F, 1 A/ μ s load step from 50% to
100% I
O
max
Transient response
Recovery time 70 μ s
V
O
over/undershoot 100 mV
V
I
= increasing 2.95 3
UVLO Undervoltage lockout V
V
I
= decreasing 2.7 2.8
Input high voltage (V
IH
) V
I
– 0.5 Open
(3)
V
Inhibit control (pin 5) Input low voltage (V
IL
) – 0.2 0.6
Input low current (I
IL
) – 10 μ A
I
I(stby)
Input standby current Pin 5 connected to GND 1 mA
F
S
Switching frequency Over V
I
and I
O
ranges 700 kHz
External input capacitance Ceramic type (C1) 47
(4)
μ F
Ceramic type (C2) 47
(5)
200
μ F
External output capacitance Nonceramic type (C3) 47
(5)
560
(6)
Equivalent series resistance (nonceramic) 4
(7)
m Ω
Per Bellcore TR-332, 50% stress,
MTBF Calculated reliability 48
10
6
Hrs
T
A
= 40 ° C, ground benign
(1) The set-point voltage tolerance is affected by the tolerance and stability of R
SET
. The stated limit is unconditionally met if R
SET
has a
tolerance of 1% with with 100 ppm/ ° C or better temperature stability.
(2) The minimum input voltage is 3 V or (V
O
+ 1.1) V, whichever is greater. A 5-V input bus is recommended for output voltages higher than
2 V.
(3) This control pin has an internal pullup to the input voltage V
I
. If it is left open circuit, the module operates when input power is applied. A
small low-leakage (<100 nA) MOSFET is recommended for control. Do not tie the inhibit pin to V
I
or to another module's inhibit pin. See
the application section for further guidance.
(4) An external 47- μ F ceramic capacitor is required across the input (V
I
and GND) for proper operation. Locate the capacitor close to the
module.
(5) An external 47- μ F ceramic capacitor is required across the output (V
O
and GND) for proper operation. Locate the capacitor close to the
module. Adding another 47 μ F of electrolytic capacitance close to the load improves the response of the regulator to load transients.
(6) This is the calculated maximum capacitance. The minimum ESR limitation often results in a lower value. See the capacitor application
information for further guidance.
(7) This is the typical ESR for all the electrolytic (nonceramic) capacitance. Use 7 m Ω as the minimum when calculating the total equivalent
series resistance (ESR) using the max-ESR values specified by the capacitor manufacturer.
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