Datasheet

D %
R orR =
U
D
499
-99.8kW
+
C
I
V
I
GND
MarginDown
Q2
Q1
+
MarginUp
0V
+V
O
+V
O
C
O
R
D
R
U
(TopView)
PTH05010W
1
2
10
7
6
54
3
GND
R
0.1W,1%
SET
L
O
A
D
9 8
PTH04040W
www.ti.com SLTS238C –SEPTEMBER 2005–REVISED JUNE 2010
MARGIN UP/DOWN CONTROLS
The PTHxx060, PTHxx010, PTHxx020, and PTHxx030 products incorporate Margin Up and Margin Down control
inputs. These controls allow the output voltage to be momentarily adjusted
(1)
, either up or down, by a nominal
5%. This provides a convenient method for dynamically testing the operation of the load circuit over its supply
margin or range. It can also be used to verify the function of supply voltage supervisors. The ±5% change is
applied to the adjusted output voltage, as set by the external resistor, R
set
at the V
o
Adjust pin.
The 5% adjustment is made by pulling the appropriate margin control input directly to the GND terminal 2. A
low-leakage open-drain device, such as an n-channel MOSFET or p-channel JFET is recommended for this
purpose
(3)
. Adjustments of less than 5% can also be accommodated by adding series resistors to the control
inputs. The value of the resistor can be selected from Table 4, or calculated using the following formula.
UP/DOWN ADJUST RESISTANCE CALCULATION
(4)
Where Δ% = The desired amount of margin adjusted in percent.
NOTES
1. The Margin Up and Margin Down controls were not intended to be activated simultaneously. If they are
activated simultaneously, the effects on the output voltage may not completely cancel, resulting in the
possibility of a higher error in the output voltage set point.
2. The ground reference should be a direct connection to the module GND at pin 7 (pin 1 for the PTHxx050).
This produces a more accurate adjustment at the load circuit terminals. The transistors Q1 and Q2 should be
located close to the regulator.
3. The Margin Up and Margin Down control inputs are not compatible with devices that source voltage. This
includes TTL logic. These are analog inputs and should only be controlled with a true open-drain device
(preferably discrete MOSFET transistor). The device selected should have low off-state leakage current.
Each input sources 8 µA when grounded, and has an open-circuit voltage of 0.8 V.
Table 4. Margin Up/Down Resistor Values
% ADJUST 5% 4% 3% 2% 1%
R
U
/ R
D
0 kΩ 24.9 kΩ 66.5 kΩ 150.0 kΩ 397.0 kΩ
Figure 18. Margin Up/Down Application Schematic
Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): PTH04040W