Datasheet

LATCHMODE
(MSB)B5
V
S+
IN+
B3
V
MID2
V
S+
IN-
B2
V
S+
B1
GAINSTROBE
B0
GND
V
S+
OUT+
GND
OUT-
V
S+
GND
1
2
3
4
5
6
7
21
20
19
18
17
16
15
13
14
12
11
10
8
22 23 24 25 26 27 28
B4
V
MID1
GND V
S+
GND GND GND PD
9
PowerPADä
PGA870
www.ti.com SBOS436A –DECEMBER 2009–REVISED FEBRUARY 2011
PIN CONFIGURATION
QFN-28
RHD PACKAGE
(TOP VIEW)
PIN ASSIGNMENTS
PIN NUMBER PIN NAME DESCRIPTION
Controls latched and unlatched acquisition of the gain control word (B0 to B5). See the application section Gain
1 LATCH MODE
Control Modes for a detailed description.
2, 6, 11, 16, 20, 25 V
S+
+5V power supply
3 IN+ Noninverting input
Buffer output for the internal midsupply reference. This point is the output of an active buffer which is not intended
4 V
MID2
to drive an external load. It should be bypassed by a 0.1-μF capacitor.
5 IN– Inverting input
7 GAIN STROBE Gain latch clock pin
8 B5 (MSB) Gain control MSB
9 B4 Gain control bit 4
10 B3 Gain control bit 3
12 B2 Gain control bit 2
13 B1 Gain control bit 1
14 B0 (LSB) Gain control bit 0
17 OUT– Inverting output
15, 18, 21, 22, 23,
GND Ground
24, 26
19 OUT+ Noninverting output
27 PD Active low power-down for device analog circuitry. Gain control CMOS circuitry is still active when PD is low.
Chip bypass pin for internal midsupply reference. This point is the midpoint of a resistive voltage divider and is not
28 V
MID1
intended to function as an input. It should be bypassed with a 0.1-μF capacitor.
Thermal Pad PowerPAD Thermal contact for heat dissipation. The thermal pad must be connected to electrical ground.
© 2009–2011, Texas Instruments Incorporated 5
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