Datasheet

PGA870
SBOS436A –DECEMBER 2009–REVISED FEBRUARY 2011 www.ti.com
ELECTRICAL CHARACTERISTICS: V
S+
= +5 V (continued)
Boldface limits are tested at +25°C.
At T
A
= +25°C, V
S+
= +5 V, differential input signal, differential V
OUT
= 2 V
PP
, R
L
= 200 Ω differential, G = 20 dB, and input and
output common-mode at internal midsupply reference, unless otherwise noted.
PGA870IRHD
TEST
PARAMETER CONDITIONS MIN TYP MAX UNITS LEVEL
(1)
OUTPUT
T
A
= +25°C 3.5 3.7 V A
Maximum output voltage high
Each output with
T
A
= –40°C to +85°C 3.4 V B
100 Ω to
T
A
= +25°C 1.3 1.5 V A
midsupply
Minimum output voltage low
T
A
= –40°C to +85°C 1.6 V B
T
A
= +25°C, R
L
= 200 Ω 4 4.8 V
PP
B
Differential output voltage swing
T
A
= –40°C to +85°C 3.6 V
PP
B
Differential output current drive T
A
= +25°C, R
L
= 20 Ω 40 50 mA
P
A
Output common-mode offset from
T
A
= +25°C, R
L
= 20 Ω –60 ±10 60 mV A
midsupply
Differential output impedance f = 100 MHz 3.5 / 87 Ω / ° B
Differential output impedance model Series R
OUT,EQ
, L
OUT,EQ
0.3 / 3.8 Ω / nH B
POWER SUPPLY
Specified operating voltage 4.75 5 5.25 V C
T
A
= +25°C 138 143 148 mA A
Quiescent current
T
A
= –40°C to +85°C 136 150 mA B
Power-supply rejection ratio (PSRR) T
A
= +25°C, Gain = 20 dB
(2)
54 76 dB A
POWER DOWN
Device power-up voltage threshold Ensured on above 2.1 V 2.1 V A
Device power-down voltage threshold Ensured off below 0.9 V 0.9 V A
T
A
= +25°C 2 4 mA A
Power-down quiescent current
T
A
= –40°C to +85°C 4.8 mA B
Forward isolation in power-down state f = 100 MHz -110 dB C
PD pin input bias current P
D
= V
S–
0.5 μA B
PD pin input impedance 20 || 0.5 kΩ || pF C
Turn-on time delay Measured to output on 16 ns C
Turn-off time delay Measured to output off 60 ns C
GAIN SETTING
Gain range –11.5 +20 dB A
Gain control: G0 to G5 6 Bits B
Gain step size –11.5 dB ≤ Gain ≤ +20 dB 0.50 dB A
Absolute gain error –0.35 ±0.05 0.35 dB A
Gain error over entire gain range
Step to step gain error –0.10 ±0.03 0.10 dB A
Gain temp coefficient 0.0018 0.0022 0.0026 dB/°C B
Gain settling time 5 ns B
DIGITAL INPUTS B0 to B5 and Latch
Digital threshold low 0.9 V A
Digital threshold high 2.1 V A
Current into/out of digital pins ±20 nA C
Data set up time to GAIN STROBE low 2.5 ns C
Data hold time after GAIN STROBE
0 ns C
low
Latency time 6.4 ns C
(2) PSRR is defined with respect to a differential output.
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