Datasheet

1
1
1
1
0
0
0
0
GainStrobe
LatchMode
GainBits
B5toB0
(MSBtoLSB)
Gain
Latchedon
GainStrobe
FallingEdge
Latchedon
GainStrobe
HighLevel
NoLatch
Follows
GainControlWord
1
1
1
1
0
0
0
0
GainStrobe
LatchMode
GainBits
B5toB0
(MSBtoLSB)
Gain
t
SU
t
HOLD
t
LATENCY
PGA870
www.ti.com SBOS436A –DECEMBER 2009–REVISED FEBRUARY 2011
Table 3 and Figure 43 show a summary table and timing diagrams of the gain modes, respectively. Figure 44
illustrates a timing diagram that defines the transitions and timing of the set-up and hold times for both
level-triggered and edge-triggered latch modes.
Figure 43. Gain Mode Timing
Figure 44. Set-Up and Hold Times: Level-Triggered and Edge-Triggered Latch Modes
© 2009–2011, Texas Instruments Incorporated 17
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