Datasheet

PGA870
www.ti.com SBOS436A –DECEMBER 2009–REVISED FEBRUARY 2011
Output Amplifier
The PGA870 has a differential, voltage-mode output stage with a differential output resistance of approximately
0.3 Ω and an inductive reactance equivalent to 3.8 nH. The common-mode output voltage has a nominal value of
V
MID2
. This output amplifier has a nominal gain of +20 dB.
The nominal load is 200 Ω, but the PGA870 can drive loads as low as 100 Ω with only minor changes to the
device distortion.
The output pins go to a high-impedance state when the device is the power-down state (that is, when PD is low).
8-bit Digital Interface
The 8-bit digital interface is composed of six bits: three MSBs that control the input attenuation and three LSBs
that control the input amplifier and buffered MUX. For more information on this parallel interface, refer to the Gain
Control and Latch Modes section.
Power Function
The PGA870 features a low-power disabled state for the analog circuitry when the power-down (PD) pin is low.
In the disabled state, the digital circuitry remains active, which allows the gain to be set before device power-up.
There is no internal circuitry to provide a nominal bias to this pin. If this pin is to be left open, it must be biased
with an external pull-up resistor.
Note that when the PGA870 is in this low-power mode, the gain can be programmed using the 8-bit digital
interface, the output pins go to a high-impedance state, and the voltage on the midsupply pins biasing the
attenuator (pin 4 and pin 28) goes to 0 V.
Gain Control and Latch Modes
The PGA870 has six bits of gain control (B5 to B0) that give an extended gain range from a maximum gain of 20
dB to a minimum gain of –11.5 dB. The LSB (B0) represents a minimum gain change (step size) of 0.5 dB, and
the LSB (B5) represents a gain change of 16 dB. The equivalent gain step size of each gain control bit is shown
in Table 1. The device voltage gain can be expressed by Equation 1:
Gain
dB
= 20 dB − 0.5 dB × (N
G
− 63) (1)
N
G
is the equivalent base-10 integer number that corresponds to the binary gain control word. A summary of the
63 possible device gains versus NG and the values of B0 to B5 are shown in Table 2.
The high and low voltage thresholds allow all of the gain control pins to be controlled by CMOS circuitry. There
are no internal pull-up resistors on the gain-control pins. If the pins are to be left open, they must be biased with
external pull-up resistors.
The PGA870 can be configured so the device gain is controlled by only the six gain bits (no latch) when the
GAIN STROBE pin and the GAIN MODE pin are both held high. In this operating mode, the device voltage gain
follows the signals on pins B0 to B5. Transients on the six gain bits can cause changes to the PGA870 gain
while in this mode, as well. To combat this possibility, the PGA870 also supports two gain modes where the gain
bit data are acquired and latched by signals on the GAIN STROBE pin.
The device is configured for a level-triggered latch when the LATCH MODE pin is high; this configuration allows
the six gain bits to be acquired and latched only on a high signal on the GAIN STROBE. When the GAIN
STROBE signal goes low, the gain-control data are latched and the PGA870 gain is independent of the six gain
bits until the GAIN STROBE goes high again.
If the PGA870 LATCH MODE pin is low, the device is configured for an edge-triggered latch that acquires and
latches the six gain-control bits only on the falling edge of the GAIN STROBE signal.
© 2009–2011, Texas Instruments Incorporated 15
Product Folder Link(s): PGA870