Datasheet

SLDU010
TI CONFIDENTIAL – NDA Restrictions
Page 9 of 50
The VOUT2 signal on the PGA400-Q1 is not connected to the DAC Output MUX. The VOUT2
signal on the P4 header is still connected to the DAC Output MUX
1 3
The TXD signal on the PGA400-Q1 is connected to the RS-232 transceiver
JP26
1 3
The TXD input of the RS-232 transceiver is not connected to the PGA400-Q1 and is open so an
external signal can be connected
1 3
The RXD signal on the PGA400-Q1 is connected to the RS-232 transceiver
JP27
1 3
The RXD input of the RS-232 transceiver is not connected to the PGA400-Q1 and is open so an
external signal can be connected
The GPIO_3 signal on the PGA400-Q1 is connected to the SCL signal on the TI-GER and also
to the P4 header
JP28
The GPIO_3 signal on the PGA400-Q1 is not connected to the SCL signal on the TI-GER. The
SCL signal from the TI-GER is still connected to the P4 header.
The GPIO_1 signal on the PGA400-Q1 is connected to the SDA signal on the TI-GER and also
to the P4 header
JP29
The GPIO_1 signal on the PGA400-Q1 is not connected to the SDA signal on the TI-GER. The
SDA signal from the TI-GER is still connected to the P4 header.
Legend: Indicates the corresponding pins that are shorted or closed.
Table 3. Jumper Setting Options
3 Sensor Inputs and Simulators
There are two main sensor Analog Front Ends (AFE) in the PGA400-Q1 sensor signal
conditions, one targeted towards resistive or voltage based sensors and one targeted for
capacitive sensors. The PGA400-Q1 EVM is equipped with simple circuits to simulate the basic
functionality of these different sensors. Below is a simplified block diagram of the sensor
simulators on the PGA400-Q1 EVM.