SLDU010 PGA400-Q1 EVM User Guide Mixed Signal Automotive Car Information Systems Read This First About This Manual This user’s guide describes the characteristics, operation, and use of the PGA400-Q1EVM. An EVM overview, GUI description, interface requirements, and complete schematic are included.
PGA400 EVM User Guide Introduction The PGA400-Q1 is a generic sensor interface IC for resistive and capacitive sensors. It features a configurable Analog Front-End (AFE) with diagnostics, Sigma-Delta ADC, 8051 microcontroller, DACs, SPI, I2C, and a One-Wire Interface (OWI). 1 Power Supply Requirements and Connections There is only one main +9VDC - +12VDC power connector on the PGA400-Q1EVM that supplies power to the entire board.
SLDU010 Configure the power supply based on the table below: Connection Voltage Current Limit VPWR +9 – +12VDC 100mA When powered, the “D30” LED should illuminate and the EVM should draw between 30 and 55mA depending on what state of operation it is in. Figure 2. Minimum Power Supply Connections to Operate the R2D2 EVM 1.
PGA400 EVM User Guide 1.2 Power Supply LEDs LEDs are installed in several places on the EVM to provide the user indication that powersupplies are connected correctly. The VDD and VP_OTP connections on the PGA400-Q1 have LEDs to indicate that power is applied. Also, there are two LEDS that indicate that the USB power supplies on the TI-GER boards are present. LED D2 Supply TI-GER 3.3V D3 TI-GER 5V D30 PGA400-Q1 VDD D31 PGA400-Q1 VP_OTP Table 1.
SLDU010 2 Jumper Settings There are several jumpers located on the board used to configure the connections to the PGA400Q1 and the rest of the EVM. Although they are installed to default settings in the factory it is recommended that the user verify that the shunts are installed to their default settings before powering on the EVM. The default settings and their effects are listed below. 2.1 Default Jumper Settings: Figure 4.
PGA400 EVM User Guide Reference JP1 JP2 JP3 JP4 JP5 JP6 JP7 JP8 JP9 JP10 JP11 JP12 JP13 JP14 JP15 JP16 JP17 JP18 JP19 JP22 JP23 JP26 JP27 JP28 JP29 Jumper Position(s) Function Closed The VDD power supply input on the PGA400-Q1 will be supplied from the +5V regulator on the EVM Open The VP_OTP power supply input on the PGA400-Q1 is not connected to the +7.
SLDU010 Table 2. Default Jumper Settings 2.1.1 Jumper Setting Options Table 3 below shows the function of each specific jumper setting on the EVM. Reference Jumper Setting Function The VDD power supply input on the PGA400-Q1 will be supplied from the +5V regulator on the EVM JP1 The VDD power supply input on the PGA400-Q1 will not be supplied from the +5V regulator on the EVM and can be connected to an external +5V power supply The VP_OTP power supply input on the PGA400-Q1 is connected to the +7.
PGA400 EVM User Guide The VIN1N input filter is connected to the DAC MUX and variable resistive bridge JP11 JP12 The VIN1N input filter is not connected to the DAC MUX and variable resistive bridge.
SLDU010 The VOUT2 signal on the PGA400-Q1 is not connected to the DAC Output MUX.
PGA400 EVM User Guide Figure 5. 3.1 Simplified Block Diagram of PGA400-Q1 Input Circuitry Resistive Bridge Sensors There are two main ways to simulate a resistive bridge sensor on the PGA400-Q1 EVM. The first is a simple resistive bridge with two variable legs that can be used to adjust the voltage to the VIN1P/VIN1N and VIN2P/VIN2N inputs. The second uses 16-bit DACs and ADCs to set and measure the voltage at the inputs.
SLDU010 Figure 6. Channel 1 Resistive Bridge Sensor Simulator 3.1.2 Buffered DAC Outputs The second way to excite the voltage inputs to the PGA400-Q1 is to use the buffered DAC outputs on the EVM. The DAC8574, a four-channel 16-bit DAC, is used to generate voltage signals that can be used to excite the VIN1P/VIN1N and VIN2P/VIN2N inputs. When the DAC MUX is set to the VIN1P/VIN1N and VIN2P/VIN2N sensor inputs, the DAC buffers over-drive the voltage that the resistive bridge was previously producing.
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SLDU010 Figure 7. DAC8574 and OPA2335 Buffers 3.1.3 Input Filters Both the buffered DAC outputs and the Resistive Bridge outputs feed through the input filter on the EVM before they connect to the inputs to the PGA400-Q1. The input filter is comprised of a common-mode and differential filter made from ferrite beads and capacitors. When the EVM is delivered to the customer, the ferrite beads L1-L4 are populated with 49Ohm resistors so that the filters work as simple RC low-pass filters.
PGA400 EVM User Guide 3.2 Capacitive Sensors There is only one way to easily simulate capacitive sensors on the PGA400-Q1 EVM. This method uses a fixed reference cap on one leg, and then a fixed cap in parallel with a variable trim cap on the other leg. The reference leg capacitance is set to 56pF, and the variable leg is adjustable from 35 – 80pF. The figure below shows the circuit for the capacitive sensor simulator. Figure 9.
SLDU010 4 PGA400-Q1 VOUT1/VOUT2 Output Circuitry There are two DAC outputs on the PGA400-Q1, VOUT1 and VOUT2, which serve as the main output for the PGA400-Q1 device. Simple circuitry including output filtering and ADC monitoring of the DAC outputs are present on the EVM. The VOUT1 output also has circuitry that is used for the OWI activation as well as the OWI communication. Figure 10. Simplified Block Diagram of PGA400-Q1 Output Circuitry 4.
PGA400 EVM User Guide Figure 11. 4.2 VOUT1/VOUT2 Output Filtering ADC Measurement of VOUT1/VOUT2 DAC Outputs The EVM comes equipped with two ADCs that are used to monitor and report the voltage at the VOUT1/VOUT2 outputs back to the GUI. The EVM uses two ADS1100, 16-bit ADCs, to monitor the two outputs. The ADCs are enabled by configuring the PGA400-Q1 DAC Output MUX to route the VOUT1/VOUT2 outputs into the ADCs. The PGA400-Q1 DAC Output MUX and the ADCs are all configurable with the GUI. 4.
SLDU010 Figure 12. 4.4 OWI Activation Circuit OWI Transceiver – VOUT1 Once the OWI transceiver in the PGA400-Q1 has been activated either by the OWI activation pulse, or by a direct SPI write the TI-GER needs to communicate with the PGA400-Q1 with the proper OWI signals. A simple circuit is used to convert the two-signal TI-GER USART (TX/RX) into the single wire OWI signal.
PGA400 EVM User Guide Figure 13. OWI Transceiver 5 PGA400-Q1 Communication Interfaces The PGA400-Q1 has several communication options including: SPI, I2C, OWI, and UART. All of these communication interfaces and related circuitry are present on the PGA400-Q1 EVM. 5.1 SPI SPI is the main communication method on the PGA400-Q1 and must be used to initially select one of the other communication methods (with the exception of the OWI activation pulse).
SLDU010 Figure 14. 5.2 SPI/I2C Communication MUX I2C I2C is the second most common protocol for communicating with the PGA400-Q1 device. The I2C communication method must be selected in the PGA400-Q1 by sending the appropriate SPI commands before the communication will work. If the GUI is used to change from SPI to I2C mode, the GUI will configure the SPI/I2C MUX to send the I2C signals to the PGA400-Q1. I2C is also used as the main communication method for the DAC and ADC peripherals on the EVM.
PGA400 EVM User Guide Figure 15. 5.3 PGA400-Q1 / EVM I2C MUX OWI During final system calibration, the OWI communication method is preferred because it allows for a three-pin sensor module (Power, GND, VOUT/OWI). The OWI communication method can be selected in the PGA400-Q1 by either sending the appropriate SPI commands to place the device in OWI mode, or by issuing the OWI activation pulse and writing software in the 8051 to switch to OWI mode when the OWI activation pulse is detected.
SLDU010 Figure 16. RS-232 Transceiver 6 Controlling the PGA400-Q1 Memory Spaces with the GUI The PGA400-Q1 EVM is controlled by the user through a PC with the TI-GER USB communication board and associated GUI. The PGA400-Q1 EVM GUI provides ways to manipulate all of the register spaces present inside the PGA400-Q1 (TEST, ESFR, EEPROM, IRAM, OTP). The following sections describe how to manipulate the register spaces. 6.
PGA400 EVM User Guide 6.1.3 SAVE GRID The “SAVE GRID” button will take the contents of the register grid and save them to a .TXT file. The data is saved in comma-separated-values format. 6.1.4 RECALL GRID The “RECALL GRID” button will open a prompt that will allow the user to select a .TXT file that was produced during the “SAVE GRID” operation and will then load the grid with the contents from the .TXT file. 6.1.
SLDU010 6.2.2 Restricted Access As described in the PGA400-Q1 datasheet, to access some of the features in the TEST register map, a special unlock sequence must be sent to register 0xFF. The Restricted Access button sends this sequence to the PGA400-Q1 device. 6.3 ESFR Registers The “ESFR” register tab only contains a grid that can be used with the functions described before to directly manipulate the “ESFR” register space.
PGA400 EVM User Guide 6.5 IRAM The IRAM tab is setup only for individual register read/writes without the use of the grid. When this tab is displayed, the “READ SELECTED / READ ALL” and “WRITE SELECTED / WRITE ALL” buttons perform the same operations respectively. 6.6 OTP The OTP tab is setup only for individual register read/writes without the use of the grid. When this tab is displayed, the “READ SELECTED / READ ALL” and “WRITE SELECTED / WRITE ALL” buttons perform the same operations respectively.
SLDU010 6.6.2 Program OTP Memory from .HEX File If the “Program OTP Memory from .HEX File” check box was checked (default) when the .HEX file was loaded into the GUI, the OTP memory will be programmed with the contents of the .HEX file. 6.6.3 Verify OTP Programming If the “Verify OTP Programming” button was also checked (default) then after the OTP memory is finished programming, the GUI will reset the MCU and then verify that the contents of the OTP memory match the .HEX file.
PGA400 EVM User Guide 7.1 ADC Conversion Result Section of the GUI In the bottom right corner of the GUI is dedicated for functions that support or directly read from the internal ADC inside the PGA400-Q1. These buttons were not put inside a tab like the rest of the buttons because it is useful to be able to read the ADC registers which modifying the AFE settings without having to switch tabs. An image along with a description of the buttons can be found below. Figure 19.
SLDU010 7.2.1 Resistive AFE Tab The resistive AFE tab is selected by default when the GUI loads. This corresponds to the default setting to have the resistive AFE selected on power-up. An image of the resistive AFE tab along with a description of the buttons can be found below. Figure 20. Resistive AFE Tab 7.2.1.1 Activate Resistive Bridge AFE The “Activate Resistive Bride AFE” button configures the PGA400-Q1 for the Resistive AFE by controlling bit 7 in ESFR 0xA7. 7.2.1.
PGA400 EVM User Guide 7.2.1.5 Stage 1 Gain Select The “Stage 1 Gain Select” combo-box controls bits 5-7 of either register 0xA1 or 0xA2 depending on the state of the “Sensor Select” combo-box 7.2.1.6 Stage 2 Gain Select The “Stage 2 Gain Select” combo-box controls bits 0-4 of either register 0xA1 or 0xA2 depending on the state of the “Sensor Select” combo-box 7.2.2 Capacitive AFE Tab The capacitive AFE tab is not activated by default when the GUI loads.
SLDU010 7.2.2.4 Trans-Z The “Trans-Z” selection boxes control the transimpedance resistance by controlling bits 0 and 1 in ESFR 0xA7. 7.2.3 ZTC and PTAT Offset Control The ZTC and PTAT Offset circuits are shared whether the user is using the PGA400-Q1 in resistive or capacitive mode, therefore they are displayed while either AFE tab is selected. An image and description of the buttons on the offset control region of the GUI are described below. Figure 22. ZTC and PTAT Offset Control 7.2.3.
PGA400 EVM User Guide 7.2.3.4 Offset PTAT Compenstation Adjust Up/Down The “Coarse” Up/Down and “Fine” Up/Down buttons are used to adjust the value of the PTAT offset register up or down in set increments. The buttons write to the PTAT offset bits in ESFRs 0xA4 or 0xA6 depending on the state of the “Sensor Select” combo-box. The “Fine” adjustments move the PTAT offset value by one, while the “Coarse” buttons move the PTAT offset value by 50. 7.
SLDU010 7.3.1 Update AFE Flags The “Update AFE Flags” button reads from ESFR 0x93 and then updates the color of the flags in the GUI accordingly. 7.3.2 Update PSMON Flags The “Update PSMON Flags” button reads from ESFRs 0x91 and 0x92 and then updates the color of the flags in the GUI accordingly. 7.4 Test MUX The Test MUX tab can be used to activate and control the settings on the analog and digital test in/out MUXes that are present inside the PGA400-Q1.
PGA400 EVM User Guide 7.4.1.1 Activate Analog Test MUX The “Activate Analog Test MUX” button disables the VOUT1/VOUT2 DACs and activates the Analog Test MUXes by controlling bits 3 and 4 of TEST register 0x10. 7.4.1.2 TIP_A / TIN_A Combo-Box The “TIP_A / TIN_A” combo-box is used to select where the TIN and TIP signals get routed inside the PGA400-Q1 by controlling TEST register 0x08. 7.4.1.
SLDU010 7.4.2.1 Activate TIP_D The “Activate TIP_D” button disables the digital test input signal by controlling bit 1 of TEST register 0x03. 7.4.2.2 Activate TOP_D The “Activate TOP_D” button disables the activates the digital test output signal by controlling bits 2 and 3 of TEST register 0x03. 7.4.2.3 TIP_D / TIN_D Combo-Box The “TIP_D / TIN_D” combo-box is used to select where the digital test input signals get routed inside the PGA400-Q1 by controlling TEST register 0x07. 7.4.2.
PGA400 EVM User Guide 7.5.1.1 DAC1 Output Read/Set The “Read” and “Set” buttons in the DAC1 region can be used to directly enter in the desired DAC1 values. The buttons either read to or write from the DAC1 ESFRs 0xB7/0xB9. 7.5.1.2 DAC1 Output Adjust Up/Down The “Coarse” Up/Down and “Fine” Up/Down buttons are used to adjust the value of the DAC1 output register up or down in set increments. The buttons write to the DAC1 output bits in ESFRs 0xB7/0xB9.
SLDU010 Figure 27. OWI GUI Tab 7.6.1 Activate OWI with Over-Voltage Drive The “Activate OWI with Over-Voltage Drive” button on the GUI initializes the OWI activation circuit by controlling the signal that drives the “Q4” BJT. Pressing the button will disable the PGA400-Q1 Output MUX, activate the +7.5V pull-up, wait roughly 200ms, then release the OWI pull-up. The 8051 must be running have code loaded into it that will send the signals to activate the OWI transceiver. 7.6.
PGA400 EVM User Guide 7.6.4 Send Sync The “Send Sync” button will send the required preliminary “Sync” pulse to flush the contents of the OWI transceiver shift buffer. 7.6.5 Write/Read Tab The bottom portion of the main OWI tab is divided between performing simple OWI writes and reads and performing OWI burst write/reads. An image of the “Write/Read” tab can be seen in the previous figure and a description of the buttons can be found below. 7.6.5.
SLDU010 7.6.6 EEPROM Burst Write/Read Tab The second tab on the bottom portion of the OWI tab is the “EEPROM Burst Write/Read” tab. This tab is used to perform the EEPROM “Burst” write/read commands that the PGA400-Q1 supports. An image of the tab along with a description of the buttons can be found below. Figure 28. EEPROM Burst Write/Read Tab 7.6.6.
PGA400 EVM User Guide 7.6.6.3 EEPROM Burst Write 2 The “EEPROM BURST WRITE 2” button will perform a burst write with the data that has been entered into the textboxes under the “Write Data” label on the right side of the tab. 7.6.6.4 EEPROM Burst Read 2 The “EEPROM BURST READ 2” button will perform a burst read and then populate the data into the textboxes under the “Read Data” with the data that has been entered into the textboxes under the “Read Data” label on the right side of the tab. 7.
SLDU010 7.7.1 Input Compare 1 Region The “Input Compare 1 Region” is used to activate and read from the Input Compare 1 peripheral in the PGA400-Q1. 7.7.1.1 Activate IC1 The “Activate IC1” button activates the Input Compare 1 function in the PGA400-Q1 by controlling bit 0 of ESFR 0xC7. 7.7.1.2 Read IC1 The “Read” button in the IC1 region is used to update the text box with the contents of the input compare registers by reading ESFRs 0xC1 and 0xC2. 7.7.1.
PGA400 EVM User Guide 7.7.3.2 Read OC1 The “Read” button in the OC1 region is used to update the text box with the contents of the output compare registers by reading ESFRs 0xC5 and 0xC6. 7.7.3.3 Set OC1 The “Set” button in the OC1 region is used to set the value in the Output Compare 1 register by writing to ESFR 0xC5 and 0xC6. 7.7.4 Output Compare 2 Region The “Output Compare 2 Region” is used to activate and set/read the Output Compare 2 peripheral in the PGA400-Q1. 7.7.4.
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SLDU010 EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards.
PGA400 EVM User Guide IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions: The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods.
FCC Interference Statement for Class B EVM devices This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
【Important Notice for Users of this Product in Japan】 】 This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product: 1. 2. 3. Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.
EVALUATION BOARD/KIT/MODULE (EVM) WARNINGS, RESTRICTIONS AND DISCLAIMERS For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished electrical equipment and not intended for consumer use.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
