Datasheet

R
4R
R
Auto
Zero
Auto
Zero
R
Auto
Zero
PGA
Diff Amp
xG
Bandgap
Reference
POR
A2
A1
A3
PGA Gain Select (1 of 8)
Range of 4 to 128
(with PGA Diff Amp Gain = 4)
RGO
Output Gain Select (1 of 7)
Range of 2 to 9
Digital Controls
SCL
PRG
SDA
x0.52
x0.83
x0.124
x0.166
INT/EXT FB Select
Alarm Register Inputs
Temp ADC
Ref Mux
Temp ADC
Internal REF
Internal
Temp Sense
16 3 10
14
13
12
7
6
8
112
9
4
5
15
1
S
Fault Monitor
Circuit
Test Logic
Temp ADC
Input Mux
Temp ADC
REF Select
Temp Select
Source
Temp ADC, PGA
(x1, x2, x4, x8)
Temp ADC Input
Mux Select
Interface and
Control Circuitry
Control Registers
Alarm Register
Offset TC Adjust and Scan TC Adjust
Look-Up Logic with Interpolation Algorithm
Output
Amplifier
Input Mux
Input Mux
Control
Coarse
Offset Adjust
Fine
Offset Adjust
Fine Gain Adjust
(16-Bit)
TEST
RFO
PGA309
V
EXC
V
EXC
V
SA
V
FB
V
SA
V
SA
V
SD
V
SD
V
REFT
V
REF
R
F
R
F
R
G
V
REF
V
REF
V
REF
V
FB
V
FB
V
OUT
V
SJ
V
IN2
V
IN1
GND
A
GND
D
V
OUT
V
INP
V
INN
V
REF
V
REF
V
EXC
V
EXC
V
OUT
V
SA
I
TEMP
7 Am
16-Bit
Zero
DAC
16-Bit
4-Bit +
Sign DAC
I Enable
TEMP
V Internal Set
(2.5V or 4.096V)
REF
V Internal Set
(2.5V or 4.096V)
REF
V Enable
EXC
REF /REF
IN OUT
TEMP
IN
TEMP
IN
7-Bit + Sign
Lin DAC
15-Bit + Sign
Temp ADC
Linearization and V
Gain Adjust
EXC
V
REF
R
SET
Gain
DAC
3-Bit
DAC
Scale
Limiter
3-Bit
DAC
Over-Scale
Limit
Under-Scale
Limit
Front-End
PGA Output
Front-End PGA
PGA309
www.ti.com SBOS292C –DECEMBER 2003–REVISED JANUARY 2011
Figure 25. Detailed Block Diagram
Copyright © 2003–2011, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): PGA309