Datasheet
V = mux_sign V + V GI + V GD GO
OUT IN Coarse_Offset Zero_DAC
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PGA309
SBOS292C –DECEMBER 2003–REVISED JANUARY 2011
www.ti.com
If this fault flag is programmed for high, then greater DIGITAL INTERFACE
than 97% ADC range will be a fault; if programmed
There are two digital interfaces on the PGA309. The
for low. then less than 3% ADC range will be a fault.
PRG pin uses a One-Wire, UART-compatible
In this configuration, the system software can be
interface with bit rates from 4.8Kbits/s to 38.4Kbits/s.
used to distinguish between over- or under-pressure
The SDA and SCL pins together form an industry
condition, which indicates an out-of-control process,
standard Two-Wire interface at clock rates from 1kHz
or a sensor fault.
to 400kHz. The external EEPROM uses the Two-Wire
interface. Communication to the PGA309 internal
POWER-UP AND NORMAL OPERATION
registers, as well as to the external EEPROM, for
programming and readback can be conducted
The PGA309 has circuitry to detect when the power
through either digital interface.
supply is applied to the PGA309, and reset the
internal registers and circuitry to an initial state. This
It is also possible to connect the One-Wire
reset also occurs when the supply is detected to be
communication pin, PRG, to the V
OUT
pin in true
invalid, so that the PGA309 is in a known state when
three-wire sensor modules and still allow for
the supply becomes valid again. The rising threshold
programming. In this mode, the PGA309 output
for this circuit is typically 2.2V and the falling
amplifier may be enabled for a set time period and
threshold is typically 1.7V. After the power supply
then disabled again to allow sharing of the PRG pin
becomes valid, the PGA309 waits for approximately
with the V
OUT
connection. This allows for both digital
25ms and then attempts to read the configuration
calibration and analog readback during sensor
data from the external EEPROM device.
calibration in a three-wire sensor module.
If the EEPROM has the proper flag set in address
The Two-Wire interface has timeout mechanisms to
locations 0 and 1, then the PGA309 continues
prevent bus lockup from occurring. The Two-Wire
reading the first part of the EEPROM; otherwise, the
master controller in the PGA309 has a mode that
PGA309 waits for one second before trying again. If
attempts to free up a stuck-at-zero SDA line by
the PGA309 detects no response from the EEPROM,
issuing SCL pulses, even when the bus is not
the PGA309 waits for one second and tries again;
indicated as idle after a timeout period has expired.
otherwise, the PGA309 tries to free the bus and waits
The timeout will only apply when the master portion
for 25ms before trying to read the EEPROM again. If
of the PGA309 is attempting to initiate a Two-Wire
a successful read of the first part of the EEPROM is
communication.
accomplished, (including valid Checksum1 data), the
PGA309 triggers the Temp ADC to measure
PGA309 TRANSFER FUNCTION
temperature. For 16-bit resolution results, the
converter takes approximately 125ms to complete a
Equation 1 shows the mathematical expression that is
conversion. Once the conversion is complete, the
used to compute the output voltage, V
OUT
. This
PGA309 begins reading the Lookup Table information
equation can also be rearranged algebraically to
from the EEPROM (second part) to calculate the
solve for different terms. For example, during
settings for the Gain DAC and Zero DAC.
calibration, this equation is rearranged to solve for
V
IN
.
The PGA309 reads the entire Lookup Table so that it
can determine if the checksum for the Lookup Table
(Checksum2) is correct. Each entry in the Lookup
(1)
Table requires approximately 500ms to read from the
Where:
EEPROM. Once the checksum is determined to be
valid, the calculated values for the Gain and Zero
mux_sign: This term changes the polarity of the
DACs are updated into their respective registers, and
input signal; value is ±1.
the output amplifier is enabled. The PGA309 then
V
IN
: The input signal for the PGA309; V
IN
1 = V
INP
,
begins looping through this entire procedure, starting
V
IN
2 = V
INN
.
with reading the EEPROM configuration registers
V
Coarse_Offset
: The coarse offset DAC output
from the first part of the EEPROM, then starting a
voltage.
new conversion on the Temp ADC, which then
GI: Input stage gain.
triggers reading the Lookup Table data from the
V
Zero_DAC
: Zero DAC output voltage.
second part of the EEPROM. This loop continues
indefinitely.
GD: Gain DAC.
GO: Output stage gain.
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