Datasheet
PGA308
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SBOS440B –JULY 2008–REVISED DECEMBER 2010
Timeout on the One-Wire Interface
ONE-WIRE OPERATION WITH 1W
CONNECTED TO V
OUT
The PGA308 includes a timeout mechanism. If
synchronization between the controller and the
In some sensor applications, it is desired to provide
PGA308 is lost for any reason, the timeout
the end user of the sensor module with three pins:
mechanism allows the One-Wire interface to reset
V
S
, GND, and Sensor Out. It is also desired in these
communication. The timeout period is set to
applications to digitally calibrate the sensor module
approximately 28ms (typical). If the timeout period
after its final assembly of sensor and electronics. The
expires between the initialization byte and the
PGA308 has a mode that allows the One-Wire
command byte, between the command byte and any
interface pin (1W) to be tied directly to the PGA308
data byte, or between any data bytes, the PGA308
output pin (V
OUT
).
resets the One-Wire interface circuitry so that it
To calibrate the PGA308 in Three-Wire configuration,
expects an initialization byte. Every time that a byte is
program the internal registers and measure the
transmitted on the single wire interface, this timeout
resulting V
OUT
. To do this while V
OUT
is connected to
period restarts.
1W requires the ability to enable and disable V
OUT
.
Thus, the 1W/V
OUT
line operates in a multiplexed
POWER-ON SEQUENCE
mode where 1W is used as a bidirectional digital
The PGA308 provides circuitry to detect when the interface while V
OUT
is disabled, and V
OUT
drives the
power supply is applied to the PGA308 and resets line as a conditioned sensor output voltage when it is
the internal registers to a known power-on reset enabled.
(POR) state. This reset also occurs whenever the
The PGA308 also provides a mode in which the
supply is invalid so that the PGA308 is set to a known
output amplifier can be enabled for a set time period
state when the supply becomes valid again. The
and then disabled again to allow sharing of the 1W
threshold for this circuit is approximately 1.7V to
pin with the V
OUT
connection. This action is
2.1V. After the power supply becomes valid, the
accomplished by writing a value to bits OEN[7:0] in
PGA308 waits for approximately 25ms, during which
the One-Wire Enable Control register (OENC). Any
V
OUT
is disabled, and then attempts to read the data
non-zero value enables the output. This non-zero
from the last valid OTP memory bank. If the memory
value is decremented every 10ms until it becomes
bank has the proper checksum, then the PGA308
zero. When this value becomes zero, V
OUT
is
RAM is loaded with the OTP data and V
OUT
enabled.
disabled and a 1s timeout begins waiting for bus
If the checksum is invalid, V
OUT
is set to disabled.
activity on the digital interface (1W pin). As long as
Unless disabled by the OWD bit in Configuration
there is activity on the 1W pin, the 1s timeout is
Register 2 (CFG2), the One-Wire interface can
continually reset. After 1s of no bus activity, the
always communicate to the PGA308 and override the
PGA308 checks for a correct checksum. If the
contents of the current RAM in use by setting the
checksum is correct, the PGA308 runs with the
appropriate SWL[2:0] bits in the Software Control
values that currently exist in RAM. If the checksum is
Register (SFTC). For applications that require
not valid, the PGA308 checks for written bank select
instant-on for V
OUT
, the NOW bit in the CFG2 register
registers in OTP in the order of BANK SEL4, BANK
can be set to '1', which eliminates the 25ms disable
SEL3, BANK SEL2 then BANK SEL1. The highest
of V
OUT
on power-up.
bank select register containing valid programmed
space data is read. The value read from this register points
to one of the seven OTP banks, which is then loaded
space
into RAM.
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