Datasheet

J5
J9
GND
J6
J7
VSN
VSP
VSON
VSOP_EXT
1.3k
R12
1.3k
R16
100p
C7
C9
10p
C5
10p
GND
GND
GND
GND
TP2
TP5
VDD VSN
VSP
VSON
VSOP
VOCM
TP10 TP11 TP13TP12
GNDGNDGND
TP6 TP7 TP9
0
R11
0
R15
DNP
C6
C8
DNP
C4
DNP
GND
GND
TP1
TP4
1
2 3 4
J1
1
2 3 4
J3
1
2 3 4
J2
1
2 3 4
J4
GND
GND
TP15
VDD
VSOP
VSOP
VSOP_EXT
VSOP_INT
VSP
GND
10k
R21
GND
C14
10u
VSOP_INT
C12
10n
GND
33.2k
R20
GND
GND
/EF
221
R17
TP3
Test Points
VSOP Source Jumper VDD Source Jumper
EF Status LED
LDOExternal Power Connections
Input Connections Output ConnectionsPGA281
VSOP
VOCM
100k
R3
100k
R4
GND
VOCM Divider
GND
C10
10n
VSN
GND
C1
10n
GND
VSP
C2
10n
VSOP
GND
GND
G4
G3
G2
G1
G0
C11
10n
VOCM
GND
C13
10u
C15
10u
C16
10u
/EF
J8
C17
10u
VDD_EXT
GND
VDD_EXT
C3
10n
INN1
15
INP1
14
VOP
9
VON
8
G4
3
G3
4
G2
5
G1
6
G0
7
VSOP
11
VSP
13
VDD
1
VSN
16
VSON
12
VOCM
10
EF
2
U1
PGA281
VDD
22
R18
22
R23
22
R19
22
R22
External VSOP
1
2
3
JMP1
1
2
3
JMP2
LDO VSOP
VDD = VSOP
External VDD
Gain Select
1
2
D2
1
2
D1
100k
R2
100k
R6
100k
R8
100k
R10
100k
R14
1
2
3
4
5
10
9
8
7
6
S1
G4
G3
G2
G1
G0
1
2
D3
VDD
1k
R1
1k
R5
1k
R7
1k
R9
1k
R13
GND
OPEN - G = 0
CLOSED - G = 1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011*
1100*
1101*
1110*
1111*
0.125 0.172
0.25
0.5
1
2
4
8
16
32
64
128
0.125
0.125
0.125
0.125
0.344
0.688
1.375
2.75
5.5
11
22
44
88
176
0.172
0.172
0.172
0.172
G3:G0 G4=0 G4=1
* Reserved
Gain Table
LTST-C190CKT
LED1
0.125 0.172
J10
1
3
D4
1
2
D5
N
N
TP14
OUT
1
FB
2
NC
3
GND
4
EN
5
NC
6
NC
7
IN
8
U2
TPS7A4101
www.ti.com PGA281EVM Hardware
2 PGA281EVM Hardware
This section discusses the PGA281EVM hardware schematics and PCB layout.
2.1 Schematic
The schematic of the PGA281EVM is shown in Figure 2.
Figure 2. PGA281EVM Schematic
3
dit.SBOU130–May 2013 PGA281EVM
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