Datasheet

PGA280
GPIO
CS
SCLK
MOSI
MISO
CS
SCLK
SDI
SDO
CS
SCLK
SDI
SDO
CS
SCLK
SDI
SDO
SPI
Master
Addressing
MUX0
MUX1
MUX2
External
MUX
A/D
Converter
ShiftRegister
orDAC
ExtendedChip-Select ExternalMUXControl
OR
PGA280
www.ti.com ................................................................................................................................................ SBOS487A –JUNE 2009–REVISED SEPTEMBER 2009
With only four isolation couplers (digital galvanic isolation) connected in the SPI wires, the SPI can provide
galvanic isolation for input and output channels. Figure 57 shows a block diagram of how to connect SPI devices
selected by the ECS (extended CS) signal.
Isolation couples or long SPI cables in harsh industrial environment are sensitive to impairments. For improved
communication integrity, the communication can be extended with a checksum byte.
Figure 57 shows an example of the GPIO pins used for both the extended chip select and special functions.
The chip select (CS) is connected to the PGA280 alone. The serial data input (SDI) and the serial clock (SCLK)
are shared connections, and are connected to all devices [PGA280, A/D converter, and the shift register or
digital-to-analog converter (DAC)]. The serial data output comes from each of the devices and are OR-connected
or sent to an OR gate, to be received by the master. An OR gate is only required if the connected devices do not
support 3-state operation. The PGA280 provides a 3-state output if not active. Pullup resistors may be required.
As mentioned previously, the GPIO pins are used to control an external multiplexer. In Figure 57, the three pins
from GPIO0, GPIO1, and GPIO2 are used as a MUX address. Two other GPIO pins are used as ECS to enable
communications with other slave devices.
Figure 57. Example for Connecting Two Additional SPI Devices Selected by ECS
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