Datasheet
CS toPGA280CS
SCLK
SDI
SDO
GPIO
PGA2803-State
CPOL=1
0xC1
Datatoexternaldevice
ECS
(1)
PGA280
SBOS487A –JUNE 2009–REVISED SEPTEMBER 2009................................................................................................................................................
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CS Mode
A special CS mode for the GPIO extends the device communications to other external SPI devices, such as data
converters or shift registers. This CS function is intended for SPI communication using four isolation couplers. To
use this mode, follow this procedure:
Configure the desired GPIO pins as outputs in Register 8, then configure the respective ECS (extended CS)
bits in Register 9.
Register 2 allows control of the clock mode by CPn (n for the individual ECS pins). CP = 1 asserts ECS after the
last negative SCLK edge of the command; CP = 0 asserts ECS after the positive SCLK, as Figure 56 shows.
Use the CS command 1100 0cccb [ccc = CS coded for 0 to 7] to activate ECS on a single GPIO pin.
Example for ECS on pin GPIO1 (CHKsum disabled):
0x4802 GPIO1 configured output (Note: GPIO may output a previously stored state; default is all zeroes)
0x4902 Assign CS (ECS) mode to GPIO1
0xC1 Single byte command to activate CS on GPIO1
(1) CPn = 0; the red edge applies if CPn = 1.
Figure 56. Timing for GPIO Pin Acting as CS (ECS) to External Device
This CS pin (ECS) stays low as long as CS to the PGA280 is held low. The PGA280 SDO is turned to a
high-impedance output (and requires external termination). The PGA280 ignores both clock and data signals
during this time. Therefore, data can be read and written to another device selected by the ECS port.
Communication is terminated by setting CS (to the PGA280) to high; this toggle also sets the port ECS to high
and terminates the I/O transfer with the other device.
Figure 56 shows the timing for the GPIO-generated ECS pulse in clock mode SPOL = 1 (SCLK is high after CS
asserts low). Register 2 allows activating SPOL = 0 by writing a '1' to the CP bit, according to SPI mode1. The
initial setting is SPOL = 1.
Mode1; set bit to '1': a positive edge of SCLK follows after ECS asserts low (CP = 0). See the red edge of the
GPIO trace in Figure 56.
Mode2; set bit to '0': a negative edge of SCLK follows after ECS asserts high (CP = 1). See the black edge of the
GPIO trace in Figure 56.
The negative edge of SCLK senses data. The positive edge of SCLK sets data on the data out line (if
applicable).
For SPI modes 0 or 3, SCLK must be inverted to indirectly sense data with the positive edge of SCLK. Figure 57
shows an example of connecting additional SPI devices, addressed by the ECS. The OR connection for SDO
can be a wired-OR if all devices provide a 3-state output option with the respective device CS (ECS) set high.
The SPI interface allows clock rates higher than 10MHz. Clock rates less than10MHz are recommended when
using the ECS mode for less critical printed circuit board (PCB) layout and timing. Observe delays and distortion
generated from isolation couplers. External drivers may be required to drive long and terminated cables.
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