Datasheet

BUFA
SDI
SCLK
CS
2.5 s/divm
5V/div
PGA280
www.ti.com ................................................................................................................................................ SBOS487A –JUNE 2009–REVISED SEPTEMBER 2009
Buffer Timing
The buffer is used to isolate fast transients from the overload protection of the high-precision amplifier. It avoids
current into the overload clamp. Fast transients result from the switching transient of a signal multiplexer or a
gain change; these transients cannot be filtered in the signal path.
The buffer can be turned on by software using the 'T' bit in the SPI command or by activating a GPIO pin. The
on-time of the buffer is set in Register 3 (BUFTIM).
If controlled by software command, the buffer turns active (indicated by BUFA shown in Figure 55) with the last
falling edge of SCLK.
Controlling an external MUX through Register 0 activates the GPIO pins after the rising edge of CS, providing an
extra delay.
Alternatively, the buffer can be controlled by GPIO4, after configuration (Register 8, bit 4 = 0, and 0x4C10). A
rising edge triggers the buffer with a delay of three to four clock cycles. If held high, the buffer [BUFA] remains
active. It is extended by a minimum of three to four clock cycles plus FLAGTIM.
The buffer active condition can be observed at GPIO5, after configuration for output and special function
(0x4820, 0x4C20). The time reference is the end of CS. The buffer is turned on with the 16th falling edge of the
SCLK and writing to Register 0 (0x6018). BUFA stays high for 6μs (BUFTIM0) after CS.
Figure 55. BUFA Timing
GPIO Operation Mode
The six GPIO port pins can be configured individually in several modes: as inputs or outputs; a special CS mode;
and a connection to the PGA280 internal special function register that contains control signals or indications. See
Table 1 for details. The GPIO can be accessed through SPI as soon as supply voltage is connected to DVDD
and DGND.
Input: Standard CMOS high-impedance input, no internal termination. Terminate externally if not used or set to
output. Note: The GPIOs are all set as inputs after a device reset.
Output: Push-pull output. Output current is derived from DVDD and from DGND. Avoid I/O activity and high
current during high-precision measurements to avoid coupled noise.
Special Function I/O: The configuration allows connecting a designated pin to the special function register
(Register 12): OSCout, SYNCin, BUFAout, BUFTin, EFout, MUX2, MUX1, and MUX0. The pin must be
configured as an input or output according to the pin function.
Example (CHKsum not enabled):
0x480B GPIO0, GPIO1. and GPIO3 set to output
0x4C0B GPIO0 and GPIO1 connected to MUX0 and MUX1, EFout connected to GPIO3. MUX0 and MUX1
are controlled from Register 0.
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Product Folder Link(s): PGA280