Datasheet

PGA280
SBOS487A –JUNE 2009–REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com
CHKsum is enabled by writing a '1' to this bit. A correct checksum is always required for enabling. Once set, all
communication to the device requires a valid checksum, until '0' is written to this bit. Alternatively, a software
reset [0x4101DD] or power-on reset can be performed to reset this function.
Register 12: Special Functions Register (Read = 0x8C00, Write = 0x4C)
Bit # D7 D6 D5 D4 D3 D2 D1 D0
Bit Name OSCout SYNCin BUFAout BUFTin EFout MUX2 MUX1 MUX0
POR Value 0 0 0 0 0 0 0 0
Bit Descriptions:
Special function pin designation: Set to '1' for activation.
OSCout: Internal oscillator connected to pin GPIO6 for output (GPIO6 configured as an output).
SYNCin: External connection for external oscillator input to pin GPIO6 (GPIO6 configured as an input).
BUFAout: Pin GPIO5 indicates a buffer active condition (if configured as an output). The BUFA output signal
is active high by default, but can be inverted to active low by BUFA Pol.
BUFTin: The current buffer can be triggered externally by pin GPIO4, if configured as an input. The
low-to-high edge of a pulse starts the buffer with a delay of three to four clock cycles. If held high, the buffer
[BUFA] remains active. It is extended by a minimum of three to four clock cycles plus the time set with
FLAGTIM.
EFout: A logic OR combination of error bits; see Register 10. This flag can control GPIO3 if this pin is
configured as an output and EFout = 1.
MUX2 to MUX0: If the GPIO pins are configured as outputs and these bits are set to '1', the GPIO pins are
controlled from Register 0 (if MUX-D = 0).
GPIO Configuration
Register priority: If GPIO pins are used, follow this procedure:
First, configure individual I/O bits as either inputs or outputs (Register 8); '0' = input, '1' = output. Bits B0 to
B6 are connected to GPIO0 to GPIO6, respectively.
Then, configure individual bits to the desired function. When configuring for output, set the Data Register
(Register 5) first to avoid glitches.
To configure the GPIO pins for the CS function (see Register 9):
• Configure ECS ('0' = disable, '1' = enable). If set to '1' and the I/O configuration is set to output as well, this
pin becomes ECS. Details of this configuration are described in GPIO Operation Mode, CS Mode.
• Configure for clock polarity (CP), relative to ECS in Register 2; see Register 9. Set this bit to '0': a negative
edge of SCLK follows ECS (CP = 1). Set this bit to '1': a positive edge of SCLK follows ECS (CP = 0).
• Configure for special function (Register 12): Special function signals can be assigned to the GPIO pins in this
manner: 0 = disable, 1 = enable. Pins xxout must be configured as outputs, and xxin must be configured as
inputs in Register 8.
• GPIO data to force (Register 5) GPIO data (1 = low, 0 = high). Forcing a bit, which is assigned to a special
function, may be stored until GPIO is enabled.
NOTE
Data may be stored in internal registers and therefore may show on a given GPIO pin
after the configuration is changed.
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