Datasheet
PGA280
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................................................................................................................................................ SBOS487A –JUNE 2009–REVISED SEPTEMBER 2009
Register 10: Configuration Register 1 (Read = 0x8A00, Write = 0x4A)
Bit # D7 D6 D5 D4 D3 D2 D1 D0
Bit Name MUX-D IARerr BUFA Pol ICAerr ED BUFA OUTerr GAINerr IOVerr
POR Value 0 0 0 0 0 0 0 0
Bit Descriptions:
MUX-D: Set this bit to '1' to disable MUX control from Register 0; set to '0' after reset.
BUFA Pol: Controls BUF active indication polarity. Set to '0' for high = active; set to '1' for low = active.
ED BUFA Suppress: Error detection is normally disabled during BUFA active. Errors are not suppressed if
ED BUFA = 1.
Error flags are logic OR-combined and connected to the ‘EFout’ in Register 12 as well as connected to the
GPIO3 output pin if configured. The EFout signal is active high. Assigned errors can be disabled individually
using this OR function, with the exception of ‘CHKerr’, by writing a '1' to the error bit position. [IARerr; ICAerr;
OUTerr; GAINerr; IOVerr]
Register 11: Configuration Register 2 (Read = 0x8B00, Write = 0x4B)
Bit # D7 D6 D5 D4 D3 D2 D1 D0
Bit Name LTD — FLGTIM3 FLGTIM2 FLGTIM1 FLGTIM0 Reserved CHKsumE
POR Value 0 0 0 1 0 0 0 0
Bit Descriptions:
LTD: Individual error signals are not latched if this bit is set to '1'. With EFout activated on GPIO3, the error
condition can be observed in real time, but error suppression time is applied. Clear errors in Register 4 after
writing '1' to this bit.
FLAGTIM0 to 3: Choose the number of clock cycles (nominally 1MHz) according to Table 3 for suppression
of the error flags in Register 4. The timeout starts after the end of BUFA. Alternatively, it can start with the
event if the buffer is not active or Register 10, bit 3 is set high. Allow delayed activation for the individual
error sources in the microsecond range.
Table 3. Error Flag Suppression Time
FLGTIM [3:0] CLOCK CYCLES
(1)
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
1001 12
1010 16
1011 24
1100 32
1101 48
1110 64
1111 127
(1) Clock cycles refer to internal clock or SYNCin; nominally 1MHz.
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