Datasheet

PGA280
www.ti.com ................................................................................................................................................ SBOS487A –JUNE 2009–REVISED SEPTEMBER 2009
Register 1: Software Reset Register (Write = 0x4101; Write with Checksum = 0x4101DD)
Bit # D7 D6 D5 D4 D3 D2 D1 D0
Bit Name — — — — — — — SftwrRst
POR Value 0 0 0 0 0 0 0 0
Bit Descriptions:
SftwrRst: Software Reset.
Setting this bit to '1' generates a system reset that has the same effect as a power-on reset. All registers are
reset to the respective default values; this bit self-clears.
Register 2: SPI: MODE Selection to GPIO-Pin (Read = 0x8200, Write = 0x012)
Bit # D7 D6 D5 D4 D3 D2 D1 D0
Bit Name — CP6 CP5 CP4 CP3 CP2 CP1 CP0
POR Value 0 0 0 0 0 0 0 0
Bit Descriptions:
CP[6:0] SPI mode1 or mode2 can be configured for each individual ECS (extended CS) output if activated in
Register 9. See CS Mode in GPIO Operation Mode for details. CP6 controls ECS6, for example. For SPI
mode1, set the respective bit to '1': a positive edge of SCLK follows CS (Clock Polarity, CP = 0). For SPI
mode2, set the respective bit to '0': a negative edge of SCLK follows CS (CP = 1). See also Figure 56.
Register 3: BUF Timeout Register (Read = 0x8300, Write = 0x43)
Bit # D7 D6 D5 D4 D3 D2 D1 D0
Bit Name — — BUFTIM5 BUFTIM4 BUFTIM3 BUFTIM2 BUFTIM1 BUFTIM0
POR Value 0 0 0 1 1 0 0 1
Bit Descriptions:
BUFTIM[5:0] Defines BUF timeout length. The LSB equivalent is 4*t CLK (nominal value is 4μs with a 1MHz
clock). Setting this register to 0x00 disables the BUF. The minimum timeout length that can be set is
approximately 6μs. The default/POR setting sets BUFA time on to 100μs. The BUFA bit of the Error Register
[D5] indicates the buffer active status. See Figure 55.
Register 4: Error Register (Read = 0x8400, Write = 0x44)
Bit # D7 D6 D5 D4 D3 D2 D1 D0
Bit Name CHKerr IARerr BUFA ICAerr EF OUTerr GAINerr IOVerr
POR Value 0 0 0 0 0 0 0 0
The Error Register flags activate whenever an error condition is detected. These flags are cleared when a '1' is
written to the error bit.
Bit Descriptions:
CHKerr: Checksum error in SPI. This bit is only active if checksum is enabled. This bit is set to '1' when the
checksum byte is incorrect.
IARerr: Input Amplifier Saturation
BUFA: Buffer Active
ICAerr: Input Clamp Active
EF: Error Flag. Logic OR combination of error bits of Register 10. This bit can be connected to GPIO3 pin if it
is configured for output (Register 8) and as a special function (Register 12).
OUTerr: Output Stage Error (allow approximately 6µs activation delay).
GAINerr: Gain Network Overload
IOerr: Input Overvoltage
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