Datasheet

PGA280
SBOS487A –JUNE 2009–REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com
REGISTER INFORMATION
REGISTER DETAILS
Register 0: Gain and External MUX Address (Read = 0x8000; Write with BUF Off = 0x40, Write with BUF
On = 0x60)
Bit # D7 D6 D5 D4 D3 D2 D1 D0
Bit Name G4 G3 G2 G1 G0 MUX2 MUX1 MUX0
POR Value 0 0 0 0 0 0 0 0
Bit Descriptions:
G4: Output stage gain setting. This setting is independent of the gain selected in the input stage and acts as
a multiplication factor to the input gain.
0 = 1V/V output gain (power-on default)
1 = 1.375V/V output gain (= 1⅜V/V)
G[3:0]: Input stage gain setting. Refer to Table 2.
MUX[2:0]: These ports can be used to control an external multiplexer.
Table 2. INPUT STAGE GAIN SETTINGS
G3 G2 G1 G0 Gain
0 0 0 0 1/8
0 0 0 1 1/4
0 0 1 0 ½
0 0 1 1 1
0 1 0 0 2
0 1 0 1 4
0 1 1 0 8
0 1 1 1 16
1 0 0 0 32
1 0 0 1 64
1 0 1 0 128
1 0 1 1 Reserved
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
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