Datasheet

Z Z Z
D7 D6 D5 D4 D3 D2 D1 D0C7
C6 C5
C4
A3
A2 A1
A0
SDO
SDI
SCLK
CS
GPX
SampledHere
Z Z Z
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
X X X X X X X X
CB7
B6 B5
B4
A3
A2 A1
A0
SDO
SDI
SCLK
CS
GPX
SampledHere
PGA280
SBOS487A –JUNE 2009–REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com
SPI Timing Diagrams (Read and Write)
(SCLK—Data—CS)
Figure 52. Write (to Device) Timing (GPX: Command Decoding); No Checksum Enabled.
With Checksum, Command Decoding Occurs After 24th Falling Edge of SCLK
Figure 53. Read (From Register) Timing (GPX: Command Decoding); No Checksum Enabled.
Falling Edge of SCLK Controls Logic
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