Datasheet
PGA280
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................................................................................................................................................ SBOS487A –JUNE 2009–REVISED SEPTEMBER 2009
Extended CS
The PGA280 can generate an extended chip select (ECS) for other devices that are connected to the same SPI
wires: SDO, SDI, and SCLK. This ECS signal redirects the SPI communication to the connected device, while
the PGA280 ignores data and SCLK. The CS signal to the PGA280 must stay low during such communication;
as soon as CS returns high, SPI communication is terminated. See the GPIO Operation Mode section for details.
Table 1. REGISTER MAP
(1)
REGISTER
(Decimal, aaaa RESET
[Hex])
(2)
(Binary) R/W B7 B6 B5 B4 B3 B2 B1 B0 DESCRIPTION VALUES
(3)
0 0000 W/R G4 G3 G2 G1 G0 MUX2 MUX1 MUX0 Gain and optional MUX register 0000 0000b
SftwrRst
1 0001 W Write-only register, soft reset, write 1 0000 0000b
Note2x
2 0010 W/R CP6 CP5 CP4 CP3 CP2 CP1 CP0 SPI-MODE selection to GPIO-pin 0000 0000b
BUFTIM BUFTIM BUFTIM
3 0011 W/R BUFTIM5 BUFTIM3 BUFTIM1 Set BUF time-out 0001 1001b
4 2 0
4 0100 W/R CHKerr IARerr BUFA ICAerr EF OUTerr GAINerr IOVerr Error Register; reset error bit: write 1 0000 0000b
GPIO Register Data force out or
5 0101 W/R GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 0000 0000b
sense
6 0110 W/R SW-A1 SW-A2 SW-B1 SW-B2 SW-C1 SW-C2 SW-D12 Input switch control 0110 0000b
7 0111 W/R SW-F1 SW-F2 SW-G1 SW-G2 Input switch control 0000 0000b
8 1000 W/R DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 Configure pin to out = 1 or in = 0 0000 0000b
9 1001 W/R ECS6 ECS5 ECS4 ECS3 ECS2 ECS1 ECS0 Extended CS mode (1 = enable) 0000 0000b
MUX-D IARerr BUFAPol ICAerr ED BUFA OUTerr GAINerr IOVerr
10 [A] 1010 W/R Various configuration settings 0000 0000b
dis dis at pin dis suppress dis dis dis
FLGTIM FLGTIM CHKsu
11 [B] 1011 W/R LTD FLGTIM3 FLGTIM1 Reserved Various configuration settings 0001 0000b
2 0 mE
12 [C] 1100 W/R OSCout SYNCin BUFAout BUFTin EFout MUX2 MUX1 MUX0 Special function register 0000 0000b
PIN GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 Register bit reference to GPIO pin
(4)
(1) Blank register bits are ignored and undefined.
(2) Registers 13 to 15 are for test purposes; read-only.
(3) Power-on reset values are SftwrRst values.
(4) Details for GPIO pin assignments are shown in Figure 54 .
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Product Folder Link(s): PGA280