Datasheet

INN1Clippedto
VSN,Ch1,5V/div
VSN
Ch2,5V/div
OutputSignal
Ch3,2V/div
OverloadErrorFlag
(IOVerr), Ch4
2V/div
25 s/divm
PGA280
www.ti.com ................................................................................................................................................ SBOS487A –JUNE 2009–REVISED SEPTEMBER 2009
Figure 51. Input Clipping: Negative Side
SPI and Register Description
The serial peripheral interface uses four wires: CS (input), clock (SCLK, input), data in (SDI, or slave data input),
and data out (SDO, or slave data output) and operates as a slave.
CS is active low; data are sampled with the negative clock edge. It is insensitive to the starting condition of SCLK
polarity (SPOL = 1 or 0). See Figure 52 and Figure 53.
The SPI communicates to the internal registers, starting with a byte for command and address. It is followed by a
single data byte (exception: 11tx 0ccc requires no data byte). The communication can include a checksum byte.
When enabled, this byte follows the last valid byte. Either power on reset or software reset (SftwrRst) disables
the checksum mode. Writing to Register 11 enables or disables checksum mode.
On a read command, the device responds with the data byte and the checksum byte. If the checksum is not
desired, setting CS to high terminates the transmission.
Multiple commands can be chained by holding CS low and sending the additional commands after the checksum
byte (if checksum is disabled, send a dummy byte). In this mode, read and write instructions can be mixed.
This interface allows clock rates up to 10MHz. Such high clock rates require careful board layout, short wire
lengths, and low parasitic capacitance and inductance. Observe delays and distortion generated from isolation
couplers. External drivers may be required to drive long and terminated cables.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): PGA280