Datasheet

C
470nF
1
C
470nF
2
C
470nF
3
C
100nF
4
R
22
1
W
R
22
2
W
R
10
3
W
R
10
4
W
+15V -15V +5V +3V
SD1
SD2
VSP VSN VSON VSOP DGND
DVDD
PGA280
SupplyConnections
PGA280
SBOS487A –JUNE 2009–REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com
Note: In this example, the Schottky diodes prevent substrate reversing. The supply voltages shown are only example
values.
Figure 50. Supply Connection Example Using RC Bypass Filters for Good Decoupling
External Clock Synchronization
The PGA280 uses an internal oscillator of 1MHz, nominally. This clock can be brought out to pin GPIO6 if
configured by the internal register setting to allow synchronization of external systems to this clock. If the
PGA280 must be controlled by an external clock, GPIO06 can be configured as an oscillator input, thus
overriding the internal oscillator. The frequency range must be within the specified range shown in the Electrical
Characteristics in order to maintain stable device performance. The clock pulse width is not critical, because it is
internally divided down; however, less than 30% deviation is recommended. The GPIO6 input assumes a
standard logic signal. Prevent overshoot at this pin, and provide approximately equal rise and fall time for the
lowest influence on offset voltage as a result of coupled noise.
Expect a small amount of additional noise during the transition from internal to external clock, or vice-versa, for
approximately eight clock periods because of phase mismatch.
Quiescent Current
The PGA280 uses internal resistor networks and switches to set the signal gain. Consequently, the current
through the resistor network may vary with the gain and signal amplitude. Under normal operation, the
gain-related current is low (less than 400μA). However, in signal overload conditions while a high gain is
selected, this amount of current can increase.
Settling Time
The PGA280 provides very low drift and low noise, and therefore allows repeatable settling to a precise value
with a negligible tail. Signal-related load and power dissipation variables have minimal effect on the device
accuracy.
Overload Recovery
Overload conditions can vary widely, and there are multiple points in an instrumentation amplifier that can be
overloaded. During input overload, the PGA280 folds the output signal partially back as a result of the differential
signal structure and summing, but the error flags indicate such fault conditions. The amplifier recovers safely
after removing the overload condition, as long as it is within the specified operating range as shown in Figure 51.
Avoid dynamic overload by using adequate signal filtering that reduces the input slew rate to the slew rate of the
amplifier. Fast signal jumps produced from multiplexed signal sources or gain changes cannot normally be
filtered, but the current buffer (BUF) stage can be activated to prevent current flowing through the input into the
protection clamp in such situations.
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Product Folder Link(s): PGA280