Datasheet

PGA280
SBOS487A –JUNE 2009–REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com
The buffers turn off automatically after a preset time (see Register 3, BUFTIM). They are activated from bit 5 ('T')
within the command byte. They can also be triggered by an external pin (BUFTin on GPIO4). The BUFA bit is
active in conjunction with the buffer, indicating that the buffer is busy (see Figure 55).
Error detection circuits observe the signal path for signal overvoltage (IOVerr), amplifier output clipping (IARerr),
and gain overload (GAINerr). The Input Clamp Activation indicator ICAerr indicates that current was conducted
into the dynamic clamp circuit. These indicators help prevent misinterpretation of the analog signal and diagnose
critical input signal conditions, such as those that occur with integrating analog-to-digital converters that may hide
momentary overloads and present inaccurate results.
The buffers (BUF) prevent current flowing from the signal source with a compromise of offset voltage. As soon as
the buffers are turned off, the amplifiers settle back to high precision. For signal measurement without
(multiplexer) switching transients, the buffer is not used.
Input Protection
The input terminals are protected with internal diodes connected to VSP and VSN. If the input signal voltage
exceeds the power-supply voltage (VSP and VSN), the current should be limited to less than 10mA to protect the
internal clamp diodes. This current-limiting can generally be accomplished with a series input resistor.
EMI Susceptibility
Amplifiers vary in susceptibility to electromagnetic interference (EMI), but good layout practices play a critical
role. EMI can generally be identified as a variation in offset voltage shifts. The PGA280 has been specifically
designed to minimize susceptibility to EMI by incorporating an internal low-pass filter. Additional EMI filters may
be required next to the signal inputs of the system, as well as known good practices such as using short traces,
low-pass filters, and damping resistors combined with parallel and shielded signal routing, depending on the end
system requirements.
Output Stage
The output stage power is connected to the low-voltage supply (normally 3V or 5V) that is used by the
subsequent signal path of the system. This design prevents overloading of the low-voltage signal path.
The output signal is fully differential around a common-mode voltage (VOCM). The VOCM input pin is typically
connected to midsupply voltage to offer the widest signal amplitude range. VOCM is a high-impedance input that
requires an external connection to a voltage within the supply boundaries. The usable voltage range for the
VOCM input is specified in the Electrical Characteristics and must be observed.
The output stage can be set to a gain of 1V/V and 1⅜V/V. It is set to 1V/V after device reset or power-on, and is
controlled by the gain multiplication factor.
Both signal outputs, VOP and VON, swing symmetrically around VOCM. The signal is represented as the voltage
between the two outputs and does not require an accurate VOCM. Therefore, the signal output does not include
ground noise or grounding errors. Noise or drift on VOCM is normally rejected by the common-mode rejection
capability of the subsequent signal stage.
The signal that passes through the output stage is internally monitored for two error conditions: clipping of the
signal to the supply rail and overcurrent. In fault conditions, an error flag bit is set (OUTerr).
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