Datasheet

PGA280
SBOS487A –JUNE 2009–REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com
FUNCTIONAL BLOCKS
Both high-impedance input amplifiers are symmetrical, and have low noise and excellent dc precision. These
amplifiers are connected to a resistor network and provide a gain range from 128V/V down to an attenuation of
⅛. The PGA280 architecture rejects common-mode offsets and noise over a wide bandwidth.
The PGA280 features additional current buffers placed in front of the precision amplifier that can be activated on
demand. When activated, these additional current buffers avoid problems that result from input current during
dynamic overloads, such as the fast signal transient that follows the channel switching from a multiplexer.
Without the use of the additional current buffers, the fast signal transient would overload the precision amplifiers
and high bias currents could flow into the protection clamp until the amplifiers recover from the overload. This
momentary current can influence the signal source or passive filters in front of the multiplexer and generate long
settling tails. Activating this current buffer avoids such an overload current pulse. The buffer disconnects
automatically after an adjustable time. For continuous signal measurement, the additional current buffers are not
used.
The switches in the input provide signal diagnostic capability and offer an auxiliary input channel (INP2 and
INN2; see Figure 44). Both channels can be switched to diagnose or test conditions, such as a ground-referred,
single-ended voltage measurement for either input. In this mode, each of the signal inputs can be observed to
analyze common-mode offsets and noise.
The primary input channel [INP1 and INN1] provides switches and current sources for a wire break test. A switch
can short both inputs. It can also discharge a filter capacitor after a wire break test, for example.
The signal inputs are diode-clamped to the supply rails. External resistors can be placed in series to the inputs to
provide overvoltage protection. Current into the input pins should be limited to ≤ 10mA.
The output stage offers a fully-differential signal around the output reference pin, VOCM. The VOCM pin is a
high-impedance input and expects an external voltage, typically close to midsupply. The 3V or 5V supply of the
converter or amplifier, following the PGA280 outputs, is normally connected to VSOP and VSON; this
configuration shares a common supply voltage and protects the circuit from overloads. The fully-differential signal
avoids coupling of noise and errors from the supply and ground, and allows large signal swing without the risk of
nonlinearities that arise when driving near the supply rails.
The PGA280 signal path has several test points for critical overload conditions. The input amplifiers detect signal
overvoltage and overload as a result of high gain. The output stage also detects clipping. These events are
filtered with adjustable suppression delays and then stored for readout. A GPIO pin can be dedicated for external
indication either as an interrupt or in a monitor mode.
A serial peripheral interface (SPI) controls the gain setting and switches, as well as the operation modes and the
GPIO port pins. The SPI allows read and write access to the internal registers. These registers contain
conditions, flags, and settings, as described in the SPI and Register Description section. They represent the gain
setting for the input stage from 128V/V to the attenuation of ⅛V/V in binary steps and the output stage gain of
1V/V and 1.375V/V (1⅜). The input MUX and switches and the input buffers are also controlled by registers.
Internal error conditions are stored and may be masked to activate an external pin in the GPIO port.
This GPIO port can be configured individually for either input or output or for a special function. In special
function mode, the port indicates an error condition, generates CS signal, controls an external MUX, and
connects to the buffer control and oscillator.
The port pin can act as a CS for an external SPI device. This mode connects other SPI devices [such as an
analog-to-digital (A/D) converter] to the primary four-wire SPI. This feature is especially desirable when using
galvanically-isolated SPI communication. An optional checksum byte further improves communications integrity.
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