PG A2 80 PGA280 www.ti.com................................................................................................................................................ SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009 Zerø-Drift, High-Voltage, Programmable Gain INSTRUMENTATION AMPLIFIER Check for Samples: PGA280 FEATURES DESCRIPTION • • • The PGA280 is a high-precision instrumentation amplifier with digitally-controllable gain and signal integrity test capability.
PGA280 SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
PGA280 www.ti.com................................................................................................................................................ SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009 ELECTRICAL CHARACTERISTICS Boldface limits apply over the specified temperature range, TA = –40°C to +105°C. At TA = +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, RL = 2.
PGA280 SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS (continued) Boldface limits apply over the specified temperature range, TA = –40°C to +105°C. At TA = +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, RL = 2.
PGA280 www.ti.com................................................................................................................................................ SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009 ELECTRICAL CHARACTERISTICS (continued) Boldface limits apply over the specified temperature range, TA = –40°C to +105°C. At TA = +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, RL = 2.
PGA280 SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.
PGA280 www.ti.com................................................................................................................................................ SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009 TYPICAL CHARACTERISTICS At TA = +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, RL = 2.5kΩ to VSOP/2 = VOCM, G = 1V/V, using internal clock, BUF inactive, VCM = 0V, and differential input and output, unless otherwise noted.
PGA280 SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, RL = 2.5kΩ to VSOP/2 = VOCM, G = 1V/V, using internal clock, BUF inactive, VCM = 0V, and differential input and output, unless otherwise noted.
PGA280 www.ti.com................................................................................................................................................ SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, RL = 2.5kΩ to VSOP/2 = VOCM, G = 1V/V, using internal clock, BUF inactive, VCM = 0V, and differential input and output, unless otherwise noted.
PGA280 SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, RL = 2.5kΩ to VSOP/2 = VOCM, G = 1V/V, using internal clock, BUF inactive, VCM = 0V, and differential input and output, unless otherwise noted.
PGA280 www.ti.com................................................................................................................................................ SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, RL = 2.5kΩ to VSOP/2 = VOCM, G = 1V/V, using internal clock, BUF inactive, VCM = 0V, and differential input and output, unless otherwise noted.
PGA280 SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, RL = 2.5kΩ to VSOP/2 = VOCM, G = 1V/V, using internal clock, BUF inactive, VCM = 0V, and differential input and output, unless otherwise noted.
PGA280 www.ti.com................................................................................................................................................ SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, RL = 2.5kΩ to VSOP/2 = VOCM, G = 1V/V, using internal clock, BUF inactive, VCM = 0V, and differential input and output, unless otherwise noted.
PGA280 SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, RL = 2.5kΩ to VSOP/2 = VOCM, G = 1V/V, using internal clock, BUF inactive, VCM = 0V, and differential input and output, unless otherwise noted.
PGA280 www.ti.com................................................................................................................................................ SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, RL = 2.5kΩ to VSOP/2 = VOCM, G = 1V/V, using internal clock, BUF inactive, VCM = 0V, and differential input and output, unless otherwise noted.
PGA280 SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, RL = 2.5kΩ to VSOP/2 = VOCM, G = 1V/V, using internal clock, BUF inactive, VCM = 0V, and differential input and output, unless otherwise noted.
PGA280 www.ti.com................................................................................................................................................ SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009 APPLICATION INFORMATION DESCRIPTION The PGA280 is a universal high-voltage instrumentation amplifier with digital gain control. It offers excellent dc precision and long-term stability using modern chopper technology with internal filters that minimize chopper-related noise.
PGA280 SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com FUNCTIONAL BLOCKS Both high-impedance input amplifiers are symmetrical, and have low noise and excellent dc precision. These amplifiers are connected to a resistor network and provide a gain range from 128V/V down to an attenuation of ⅛.
PGA280 www.ti.com................................................................................................................................................ SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009 Input Switch Network Figure 44 shows the arrangement of the input switches. They are controlled individually via the digital SPI. The switches B1b, B2b, A1b, and A2b are controlled automatically with the buffer (BUF) operation.
PGA280 SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com Programmable gain amplifiers such as the PGA280 use internal resistors to set the gain. Consequently, quiescent current is increased by the current that passes through these resistors. The largest amplitude could increase the supply current by ±0.4mA.
PGA280 www.ti.com................................................................................................................................................
PGA280 SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com The buffers turn off automatically after a preset time (see Register 3, BUFTIM). They are activated from bit 5 ('T') within the command byte. They can also be triggered by an external pin (BUFTin on GPIO4).
PGA280 www.ti.com................................................................................................................................................ SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009 Output Filter The PGA280 uses chopper technology for excellent dc stability over temperature and life of operation. It also avoids 1/f frequency (flicker) noise, and therefore enables both high resolution and high repeatability for dc measurements.
PGA280 SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.
PGA280 www.ti.com................................................................................................................................................ SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009 CheckSum Error (CRCerr) SPI communication can include a checksum byte for increased data integrity, when enabled. It is especially useful for an isolated SPI. This error detection is only active with the checksum activated. See the Checksum section for details.
PGA280 SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com +15V R1 22W +5V -15V C1 470nF R2 22W C2 470nF SD1 C3 470nF +3V R3 10W C4 100nF R4 10W SD2 VSP VSN VSON VSOP DGND DVDD PGA280 Supply Connections Note: In this example, the Schottky diodes prevent substrate reversing. The supply voltages shown are only example values. Figure 50.
PGA280 www.ti.com................................................................................................................................................ SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009 Overload Error Flag (IOVerr), Ch 4 2V/div Output Signal Ch 3, 2V/div VSN Ch 2, 5V/div INN1 Clipped to VSN, Ch 1, 5V/div 25ms/div Figure 51.
PGA280 SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com COMMAND STRUCTURE AND REGISTER OVERVIEW Bit 7 is the most significant bit (MSB); bit 0 is the least significant bit (LSB). Binary numbers are denoted with 'b'. 'aaaa' is used to denote the encoded register pointer, 0000b to 1111b. 'T' denotes the buffer trigger bit.
PGA280 www.ti.com................................................................................................................................................ SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009 Extended CS The PGA280 can generate an extended chip select (ECS) for other devices that are connected to the same SPI wires: SDO, SDI, and SCLK. This ECS signal redirects the SPI communication to the connected device, while the PGA280 ignores data and SCLK.
PGA280 SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com SPI Timing Diagrams (Read and Write) (SCLK—Data—CS) SDO Z Z C7 SDI C6 C5 C4 A3 A2 A1 Z A0 D7 D6 D5 D4 D3 D2 D1 D0 SCLK CS GPX Sampled Here Figure 52. Write (to Device) Timing (GPX: Command Decoding); No Checksum Enabled.
PGA280 www.ti.com................................................................................................................................................ SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009 GPIO Pin Reference As shown in Figure 54, the PGA280 has seven multi-function pins labeled GPIO0 through GPIO6. These pins can function as general purpose input-output (GPIO) pins either to read a digital input or to output a digital signal as an interrupt or control.
PGA280 SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.
PGA280 www.ti.com................................................................................................................................................ SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009 Register 1: Software Reset Register (Write = 0x4101; Write with Checksum = 0x4101DD) Bit # D7 D6 D5 D4 D3 D2 D1 D0 Bit Name — — — — — — — SftwrRst POR Value 0 0 0 0 0 0 0 0 Bit Descriptions: SftwrRst: Software Reset.
PGA280 SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com Register 5: GPIO Register (Read = 0x8500, Write = 0x45) Bit # D7 D6 D5 D4 D3 D2 D1 D0 Bit Name — GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 POR Value 0 0 0 0 0 0 0 0 Bit Descriptions: GPIO[6:0]: The GPIO bits correspond to GPIO6 through GPIO0, respectively.
PGA280 www.ti.com................................................................................................................................................
PGA280 SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com CHKsum is enabled by writing a '1' to this bit. A correct checksum is always required for enabling. Once set, all communication to the device requires a valid checksum, until '0' is written to this bit.
PGA280 www.ti.com................................................................................................................................................ SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009 Buffer Timing The buffer is used to isolate fast transients from the overload protection of the high-precision amplifier. It avoids current into the overload clamp.
PGA280 SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com CS Mode A special CS mode for the GPIO extends the device communications to other external SPI devices, such as data converters or shift registers. This CS function is intended for SPI communication using four isolation couplers.
PGA280 www.ti.com................................................................................................................................................ SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009 With only four isolation couplers (digital galvanic isolation) connected in the SPI wires, the SPI can provide galvanic isolation for input and output channels. Figure 57 shows a block diagram of how to connect SPI devices selected by the ECS (extended CS) signal.
PGA280 SBOS487A – JUNE 2009 – REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com Checksum SPI communication can be secured by adding a checksum byte to the write and read data. If this mode is activated by setting CHKsumE (bit 0 in Register 11), the PGA280 expects a valid checksum; otherwise, the device ignores the received data and sets CHKerr in Register 4.
PACKAGE OPTION ADDENDUM www.ti.
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