Datasheet

PIN CONFIGURATION
PGA2505
1
2
3
4
5
24
23
22
21
20
V +
IN
V -
IN
V IN
COM
C
S11
C
S12
C
S21
C
S22
VA-
VA+
V +
OUT
V -
OUT
VA-
AGND
GPO1
GPO2
GPO3
OVR
DGND
SDI
CS
SCLK
SDO
VD-
6
7
8
9
10
11
12
19
18
17
16
15
14
13
GPO4
PIN ASSIGNMENTS
PGA2505
www.ti.com ......................................................................................................................................................... SBOS396B – MARCH 2009 – REVISED JUNE 2009
DB PACKAGE
SSOP-24
(TOP VIEW)
TERMINAL
NAME PIN# DESCRIPTION
AGND 1 Analog Ground
GPO1 2 General-Purpose CMOS Logic Output
GPO2 3 General-Purpose CMOS Logic Output
GPO3 4 General-Purpose CMOS Logic Output
GPO4 5 General-Purpose CMOS Logic Output
OVR 6 Over Range Output (Active High)
DGND 7 Digital Ground
SDI 8 Serial Data Input
CS 9 Chip Select Input (Active Low)
SCLK 10 Serial Data Clock Input
SDO 11 Serial Data Output
VD – 12 – 5V Digital Supply
VA – 13 – 5V Analog Supply
V
OUT
– 14 Inverting Analog Output
V
OUT
+ 15 Noninverting Analog Output
VA+ 16 +5V Analog Supply
VA – 17 – 5V Analog Supply
C
S22
18 External DC Servo Capacitor #2, Terminal 2
C
S21
19 External DC Servo Capacitor #2, Terminal 1
C
S12
20 External DC Servo Capacitor #1, Terminal 2
C
S11
21 External DC Servo Capacitor #1, Terminal 1
V
COM
IN 22 Common Mode Voltage Input, 0V to +2.5V
V
IN
– 23 Inverting Analog Input
V
IN
+ 24 Noninverting Analog Input
Copyright © 2009, Texas Instruments Incorporated 5
Product Folder Link(s): PGA2505