Datasheet

SWITCHING CHARACTERISTICS
TIMING REQUIREMENTS
SCLK
SDI
SDO
t
CSO
MSB
MSB
t
CFDO
t
CSCR
t
SDS
t
SDH
t
CFCS
t
CSZ
CS
PGA2505
SBOS396B – MARCH 2009 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com
Over operating free-air temperature range (unless otherwise noted).
PGA2505
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
SCLK
Serial clock (SCLK) frequency 0 6.25 MHz
t
PH
Serial clock (SCLK) pulse width low 80 ns
t
PL
Serial clock (SCLK) pulse width high 80 ns
Over operating free-air temperature range (unless otherwise noted).
PGA2505
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT TIMING
t
SDS
SDI setup time 20 ns
t
SDH
SDI hold time 20 ns
t
CSCR
CS falling to SCLK rising 90 ns
t
CFCS
SCLK falling to CS rising 35 ns
OUTPUT TIMING
t
CSO
CS low to SDO active 35 ns
t
CFDO
SCLK falling to SDO data valid 60 ns
t
CSZ
CS high to SDO high impedance 100 ns
SERIAL PORT TIMING DIAGRAM
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Product Folder Link(s): PGA2505